2017-10-20 17:35:48 +01:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir_builder.h"
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2018-01-26 07:06:11 +00:00
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#include "util/format_rgb9e5.h"
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2017-10-20 17:35:48 +01:00
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static inline nir_ssa_def *
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nir_shift(nir_builder *b, nir_ssa_def *value, int left_shift)
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{
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if (left_shift > 0)
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return nir_ishl(b, value, nir_imm_int(b, left_shift));
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else if (left_shift < 0)
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return nir_ushr(b, value, nir_imm_int(b, -left_shift));
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else
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return value;
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}
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static inline nir_ssa_def *
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nir_mask_shift(struct nir_builder *b, nir_ssa_def *src,
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uint32_t mask, int left_shift)
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{
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return nir_shift(b, nir_iand(b, src, nir_imm_int(b, mask)), left_shift);
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}
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static inline nir_ssa_def *
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nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,
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uint32_t src_mask, int src_left_shift)
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{
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return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
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}
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static inline nir_ssa_def *
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nir_format_unpack_uint(nir_builder *b, nir_ssa_def *packed,
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const unsigned *bits, unsigned num_components)
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{
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assert(num_components >= 1 && num_components <= 4);
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nir_ssa_def *comps[4];
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if (bits[0] >= packed->bit_size) {
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assert(bits[0] == packed->bit_size);
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assert(num_components == 1);
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return packed;
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}
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unsigned offset = 0;
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for (unsigned i = 0; i < num_components; i++) {
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assert(bits[i] < 32);
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nir_ssa_def *mask = nir_imm_int(b, (1u << bits[i]) - 1);
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comps[i] = nir_iand(b, nir_shift(b, packed, -offset), mask);
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offset += bits[i];
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}
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assert(offset <= packed->bit_size);
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return nir_vec(b, comps, num_components);
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}
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static inline nir_ssa_def *
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nir_format_pack_uint_unmasked(nir_builder *b, nir_ssa_def *color,
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const unsigned *bits, unsigned num_components)
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{
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assert(num_components >= 1 && num_components <= 4);
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nir_ssa_def *packed = nir_imm_int(b, 0);
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unsigned offset = 0;
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for (unsigned i = 0; i < num_components; i++) {
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packed = nir_ior(b, packed, nir_shift(b, nir_channel(b, color, i),
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offset));
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offset += bits[i];
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}
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assert(offset <= packed->bit_size);
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return packed;
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}
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static inline nir_ssa_def *
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nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,
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const unsigned *bits, unsigned num_components)
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{
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nir_const_value mask;
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for (unsigned i = 0; i < num_components; i++) {
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assert(bits[i] < 32);
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mask.u32[i] = (1u << bits[i]) - 1;
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}
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nir_ssa_def *mask_imm = nir_build_imm(b, num_components, 32, mask);
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return nir_format_pack_uint_unmasked(b, nir_iand(b, color, mask_imm),
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bits, num_components);
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}
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2018-01-26 06:52:37 +00:00
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static inline nir_ssa_def *
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nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)
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{
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nir_ssa_def *linear = nir_fmul(b, c, nir_imm_float(b, 12.92f));
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nir_ssa_def *curved =
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nir_fsub(b, nir_fmul(b, nir_imm_float(b, 1.055f),
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nir_fpow(b, c, nir_imm_float(b, 1.0 / 2.4))),
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nir_imm_float(b, 0.055f));
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return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 0.0031308f)),
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linear, curved));
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}
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static inline nir_ssa_def *
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nir_format_srgb_to_linear(nir_builder *b, nir_ssa_def *c)
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{
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nir_ssa_def *linear = nir_fdiv(b, c, nir_imm_float(b, 12.92f));
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nir_ssa_def *curved =
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nir_fpow(b, nir_fdiv(b, nir_fadd(b, c, nir_imm_float(b, 0.055f)),
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nir_imm_float(b, 1.055f)),
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nir_imm_float(b, 2.4f));
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return nir_fsat(b, nir_bcsel(b, nir_fge(b, nir_imm_float(b, 0.04045f), c),
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linear, curved));
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}
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2018-01-26 06:32:16 +00:00
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static inline nir_ssa_def *
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nir_format_unpack_11f11f10f(nir_builder *b, nir_ssa_def *packed)
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{
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nir_ssa_def *chans[3];
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chans[0] = nir_mask_shift(b, packed, 0x000007ff, 4);
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chans[1] = nir_mask_shift(b, packed, 0x003ff100, -7);
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chans[2] = nir_mask_shift(b, packed, 0xffc00000, -17);
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for (unsigned i = 0; i < 3; i++)
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chans[i] = nir_unpack_half_2x16_split_x(b, chans[i]);
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return nir_vec(b, chans, 3);
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}
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static inline nir_ssa_def *
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nir_format_pack_r11g11b10f(nir_builder *b, nir_ssa_def *color)
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{
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/* 10 and 11-bit floats are unsigned. Clamp to non-negative */
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nir_ssa_def *clamped = nir_fmax(b, color, nir_imm_float(b, 0));
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nir_ssa_def *undef = nir_ssa_undef(b, 1, color->bit_size);
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nir_ssa_def *p1 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 0),
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nir_channel(b, clamped, 1));
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nir_ssa_def *p2 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 2),
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undef);
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/* A 10 or 11-bit float has the same exponent as a 16-bit float but with
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* fewer mantissa bits and no sign bit. All we have to do is throw away
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* the sign bit and the bottom mantissa bits and shift it into place.
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*/
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nir_ssa_def *packed = nir_imm_int(b, 0);
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packed = nir_mask_shift_or(b, packed, p1, 0x00007ff0, -4);
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packed = nir_mask_shift_or(b, packed, p1, 0x7ff00000, -9);
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packed = nir_mask_shift_or(b, packed, p2, 0x00007fe0, 17);
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return packed;
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}
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2018-01-26 07:06:11 +00:00
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static inline nir_ssa_def *
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nir_format_pack_r9g9b9e5(nir_builder *b, nir_ssa_def *color)
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{
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/* See also float3_to_rgb9e5 */
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/* First, we need to clamp it to range. */
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nir_ssa_def *clamped = nir_fmin(b, color, nir_imm_float(b, MAX_RGB9E5));
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/* Get rid of negatives and NaN */
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clamped = nir_bcsel(b, nir_ult(b, nir_imm_int(b, 0x7f800000), color),
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nir_imm_float(b, 0), clamped);
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/* maxrgb.u = MAX3(rc.u, gc.u, bc.u); */
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nir_ssa_def *maxu = nir_umax(b, nir_channel(b, clamped, 0),
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nir_umax(b, nir_channel(b, clamped, 1),
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nir_channel(b, clamped, 2)));
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/* maxrgb.u += maxrgb.u & (1 << (23-9)); */
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maxu = nir_iadd(b, maxu, nir_iand(b, maxu, nir_imm_int(b, 1 << 14)));
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/* exp_shared = MAX2((maxrgb.u >> 23), -RGB9E5_EXP_BIAS - 1 + 127) +
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* 1 + RGB9E5_EXP_BIAS - 127;
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*/
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nir_ssa_def *exp_shared =
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nir_iadd(b, nir_umax(b, nir_ushr(b, maxu, nir_imm_int(b, 23)),
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nir_imm_int(b, -RGB9E5_EXP_BIAS - 1 + 127)),
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nir_imm_int(b, 1 + RGB9E5_EXP_BIAS - 127));
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/* revdenom_biasedexp = 127 - (exp_shared - RGB9E5_EXP_BIAS -
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* RGB9E5_MANTISSA_BITS) + 1;
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*/
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nir_ssa_def *revdenom_biasedexp =
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nir_isub(b, nir_imm_int(b, 127 + RGB9E5_EXP_BIAS +
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RGB9E5_MANTISSA_BITS + 1),
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exp_shared);
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/* revdenom.u = revdenom_biasedexp << 23; */
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nir_ssa_def *revdenom =
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nir_ishl(b, revdenom_biasedexp, nir_imm_int(b, 23));
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/* rm = (int) (rc.f * revdenom.f);
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* gm = (int) (gc.f * revdenom.f);
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* bm = (int) (bc.f * revdenom.f);
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*/
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nir_ssa_def *mantissa =
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nir_f2i32(b, nir_fmul(b, clamped, revdenom));
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/* rm = (rm & 1) + (rm >> 1);
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* gm = (gm & 1) + (gm >> 1);
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* bm = (bm & 1) + (bm >> 1);
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*/
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mantissa = nir_iadd(b, nir_iand(b, mantissa, nir_imm_int(b, 1)),
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nir_ushr(b, mantissa, nir_imm_int(b, 1)));
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nir_ssa_def *packed = nir_channel(b, mantissa, 0);
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packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 1), ~0, 9);
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packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 2), ~0, 18);
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packed = nir_mask_shift_or(b, packed, exp_shared, ~0, 27);
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return packed;
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}
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