640 lines
19 KiB
C
640 lines
19 KiB
C
/*
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* Copyright © 2014 Connor Abbott
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir_instr_set.h"
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#include "nir_vla.h"
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#define HASH(hash, data) _mesa_fnv32_1a_accumulate((hash), (data))
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static uint32_t
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hash_src(uint32_t hash, const nir_src *src)
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{
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assert(src->is_ssa);
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hash = HASH(hash, src->ssa);
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return hash;
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}
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static uint32_t
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hash_alu_src(uint32_t hash, const nir_alu_src *src, unsigned num_components)
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{
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hash = HASH(hash, src->abs);
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hash = HASH(hash, src->negate);
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for (unsigned i = 0; i < num_components; i++)
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hash = HASH(hash, src->swizzle[i]);
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hash = hash_src(hash, &src->src);
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return hash;
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}
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static uint32_t
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hash_alu(uint32_t hash, const nir_alu_instr *instr)
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{
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hash = HASH(hash, instr->op);
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hash = HASH(hash, instr->dest.dest.ssa.num_components);
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hash = HASH(hash, instr->dest.dest.ssa.bit_size);
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/* We explicitly don't hash instr->dest.dest.exact */
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if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_COMMUTATIVE) {
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assert(nir_op_infos[instr->op].num_inputs == 2);
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uint32_t hash0 = hash_alu_src(hash, &instr->src[0],
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nir_ssa_alu_instr_src_components(instr, 0));
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uint32_t hash1 = hash_alu_src(hash, &instr->src[1],
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nir_ssa_alu_instr_src_components(instr, 1));
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/* For commutative operations, we need some commutative way of
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* combining the hashes. One option would be to XOR them but that
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* means that anything with two identical sources will hash to 0 and
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* that's common enough we probably don't want the guaranteed
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* collision. Either addition or multiplication will also work.
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*/
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hash = hash0 * hash1;
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} else {
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for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
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hash = hash_alu_src(hash, &instr->src[i],
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nir_ssa_alu_instr_src_components(instr, i));
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}
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}
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return hash;
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}
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static uint32_t
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hash_deref(uint32_t hash, const nir_deref_instr *instr)
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{
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hash = HASH(hash, instr->deref_type);
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hash = HASH(hash, instr->mode);
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hash = HASH(hash, instr->type);
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if (instr->deref_type == nir_deref_type_var)
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return HASH(hash, instr->var);
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hash = hash_src(hash, &instr->parent);
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switch (instr->deref_type) {
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case nir_deref_type_struct:
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hash = HASH(hash, instr->strct.index);
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break;
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case nir_deref_type_array:
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case nir_deref_type_ptr_as_array:
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hash = hash_src(hash, &instr->arr.index);
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break;
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case nir_deref_type_cast:
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hash = HASH(hash, instr->cast.ptr_stride);
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break;
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case nir_deref_type_var:
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case nir_deref_type_array_wildcard:
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/* Nothing to do */
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break;
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default:
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unreachable("Invalid instruction deref type");
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}
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return hash;
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}
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static uint32_t
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hash_load_const(uint32_t hash, const nir_load_const_instr *instr)
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{
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hash = HASH(hash, instr->def.num_components);
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if (instr->def.bit_size == 1) {
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for (unsigned i = 0; i < instr->def.num_components; i++) {
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uint8_t b = instr->value.b[i];
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hash = HASH(hash, b);
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}
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} else {
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unsigned size = instr->def.num_components * (instr->def.bit_size / 8);
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hash = _mesa_fnv32_1a_accumulate_block(hash, instr->value.f32, size);
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}
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return hash;
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}
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static int
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cmp_phi_src(const void *data1, const void *data2)
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{
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nir_phi_src *src1 = *(nir_phi_src **)data1;
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nir_phi_src *src2 = *(nir_phi_src **)data2;
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return src1->pred - src2->pred;
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}
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static uint32_t
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hash_phi(uint32_t hash, const nir_phi_instr *instr)
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{
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hash = HASH(hash, instr->instr.block);
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/* sort sources by predecessor, since the order shouldn't matter */
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unsigned num_preds = instr->instr.block->predecessors->entries;
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NIR_VLA(nir_phi_src *, srcs, num_preds);
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unsigned i = 0;
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nir_foreach_phi_src(src, instr) {
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srcs[i++] = src;
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}
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qsort(srcs, num_preds, sizeof(nir_phi_src *), cmp_phi_src);
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for (i = 0; i < num_preds; i++) {
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hash = hash_src(hash, &srcs[i]->src);
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hash = HASH(hash, srcs[i]->pred);
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}
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return hash;
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}
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static uint32_t
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hash_intrinsic(uint32_t hash, const nir_intrinsic_instr *instr)
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{
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const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
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hash = HASH(hash, instr->intrinsic);
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if (info->has_dest) {
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hash = HASH(hash, instr->dest.ssa.num_components);
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hash = HASH(hash, instr->dest.ssa.bit_size);
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}
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hash = _mesa_fnv32_1a_accumulate_block(hash, instr->const_index,
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info->num_indices
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* sizeof(instr->const_index[0]));
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return hash;
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}
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static uint32_t
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hash_tex(uint32_t hash, const nir_tex_instr *instr)
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{
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hash = HASH(hash, instr->op);
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hash = HASH(hash, instr->num_srcs);
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for (unsigned i = 0; i < instr->num_srcs; i++) {
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hash = HASH(hash, instr->src[i].src_type);
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hash = hash_src(hash, &instr->src[i].src);
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}
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hash = HASH(hash, instr->coord_components);
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hash = HASH(hash, instr->sampler_dim);
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hash = HASH(hash, instr->is_array);
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hash = HASH(hash, instr->is_shadow);
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hash = HASH(hash, instr->is_new_style_shadow);
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unsigned component = instr->component;
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hash = HASH(hash, component);
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for (unsigned i = 0; i < 4; ++i)
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for (unsigned j = 0; j < 2; ++j)
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hash = HASH(hash, instr->tg4_offsets[i][j]);
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hash = HASH(hash, instr->texture_index);
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hash = HASH(hash, instr->texture_array_size);
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hash = HASH(hash, instr->sampler_index);
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return hash;
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}
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/* Computes a hash of an instruction for use in a hash table. Note that this
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* will only work for instructions where instr_can_rewrite() returns true, and
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* it should return identical hashes for two instructions that are the same
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* according nir_instrs_equal().
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*/
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static uint32_t
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hash_instr(const void *data)
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{
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const nir_instr *instr = data;
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uint32_t hash = _mesa_fnv32_1a_offset_bias;
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switch (instr->type) {
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case nir_instr_type_alu:
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hash = hash_alu(hash, nir_instr_as_alu(instr));
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break;
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case nir_instr_type_deref:
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hash = hash_deref(hash, nir_instr_as_deref(instr));
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break;
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case nir_instr_type_load_const:
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hash = hash_load_const(hash, nir_instr_as_load_const(instr));
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break;
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case nir_instr_type_phi:
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hash = hash_phi(hash, nir_instr_as_phi(instr));
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break;
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case nir_instr_type_intrinsic:
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hash = hash_intrinsic(hash, nir_instr_as_intrinsic(instr));
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break;
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case nir_instr_type_tex:
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hash = hash_tex(hash, nir_instr_as_tex(instr));
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break;
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default:
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unreachable("Invalid instruction type");
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}
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return hash;
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}
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bool
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nir_srcs_equal(nir_src src1, nir_src src2)
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{
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if (src1.is_ssa) {
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if (src2.is_ssa) {
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return src1.ssa == src2.ssa;
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} else {
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return false;
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}
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} else {
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if (src2.is_ssa) {
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return false;
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} else {
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if ((src1.reg.indirect == NULL) != (src2.reg.indirect == NULL))
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return false;
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if (src1.reg.indirect) {
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if (!nir_srcs_equal(*src1.reg.indirect, *src2.reg.indirect))
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return false;
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}
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return src1.reg.reg == src2.reg.reg &&
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src1.reg.base_offset == src2.reg.base_offset;
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}
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}
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}
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bool
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nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2,
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unsigned src1, unsigned src2)
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{
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if (alu1->src[src1].abs != alu2->src[src2].abs ||
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alu1->src[src1].negate != alu2->src[src2].negate)
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return false;
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for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++) {
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if (alu1->src[src1].swizzle[i] != alu2->src[src2].swizzle[i])
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return false;
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}
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return nir_srcs_equal(alu1->src[src1].src, alu2->src[src2].src);
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}
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/* Returns "true" if two instructions are equal. Note that this will only
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* work for the subset of instructions defined by instr_can_rewrite(). Also,
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* it should only return "true" for instructions that hash_instr() will return
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* the same hash for (ignoring collisions, of course).
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*/
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static bool
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nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2)
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{
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if (instr1->type != instr2->type)
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return false;
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switch (instr1->type) {
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case nir_instr_type_alu: {
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nir_alu_instr *alu1 = nir_instr_as_alu(instr1);
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nir_alu_instr *alu2 = nir_instr_as_alu(instr2);
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if (alu1->op != alu2->op)
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return false;
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/* TODO: We can probably acutally do something more inteligent such
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* as allowing different numbers and taking a maximum or something
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* here */
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if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components)
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return false;
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if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size)
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return false;
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/* We explicitly don't hash instr->dest.dest.exact */
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if (nir_op_infos[alu1->op].algebraic_properties & NIR_OP_IS_COMMUTATIVE) {
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assert(nir_op_infos[alu1->op].num_inputs == 2);
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return (nir_alu_srcs_equal(alu1, alu2, 0, 0) &&
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nir_alu_srcs_equal(alu1, alu2, 1, 1)) ||
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(nir_alu_srcs_equal(alu1, alu2, 0, 1) &&
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nir_alu_srcs_equal(alu1, alu2, 1, 0));
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} else {
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for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) {
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if (!nir_alu_srcs_equal(alu1, alu2, i, i))
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return false;
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}
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}
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return true;
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}
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case nir_instr_type_deref: {
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nir_deref_instr *deref1 = nir_instr_as_deref(instr1);
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nir_deref_instr *deref2 = nir_instr_as_deref(instr2);
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if (deref1->deref_type != deref2->deref_type ||
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deref1->mode != deref2->mode ||
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deref1->type != deref2->type)
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return false;
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if (deref1->deref_type == nir_deref_type_var)
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return deref1->var == deref2->var;
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if (!nir_srcs_equal(deref1->parent, deref2->parent))
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return false;
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switch (deref1->deref_type) {
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case nir_deref_type_struct:
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if (deref1->strct.index != deref2->strct.index)
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return false;
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break;
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case nir_deref_type_array:
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case nir_deref_type_ptr_as_array:
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if (!nir_srcs_equal(deref1->arr.index, deref2->arr.index))
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return false;
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break;
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case nir_deref_type_cast:
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if (deref1->cast.ptr_stride != deref2->cast.ptr_stride)
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return false;
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break;
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case nir_deref_type_var:
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case nir_deref_type_array_wildcard:
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/* Nothing to do */
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break;
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default:
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unreachable("Invalid instruction deref type");
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}
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return true;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex1 = nir_instr_as_tex(instr1);
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nir_tex_instr *tex2 = nir_instr_as_tex(instr2);
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if (tex1->op != tex2->op)
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return false;
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if (tex1->num_srcs != tex2->num_srcs)
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return false;
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for (unsigned i = 0; i < tex1->num_srcs; i++) {
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if (tex1->src[i].src_type != tex2->src[i].src_type ||
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!nir_srcs_equal(tex1->src[i].src, tex2->src[i].src)) {
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return false;
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}
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}
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if (tex1->coord_components != tex2->coord_components ||
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tex1->sampler_dim != tex2->sampler_dim ||
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tex1->is_array != tex2->is_array ||
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tex1->is_shadow != tex2->is_shadow ||
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tex1->is_new_style_shadow != tex2->is_new_style_shadow ||
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tex1->component != tex2->component ||
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tex1->texture_index != tex2->texture_index ||
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tex1->texture_array_size != tex2->texture_array_size ||
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tex1->sampler_index != tex2->sampler_index) {
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return false;
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}
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if (memcmp(tex1->tg4_offsets, tex2->tg4_offsets,
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sizeof(tex1->tg4_offsets)))
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return false;
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return true;
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}
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case nir_instr_type_load_const: {
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nir_load_const_instr *load1 = nir_instr_as_load_const(instr1);
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nir_load_const_instr *load2 = nir_instr_as_load_const(instr2);
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if (load1->def.num_components != load2->def.num_components)
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return false;
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if (load1->def.bit_size != load2->def.bit_size)
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return false;
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if (load1->def.bit_size == 1) {
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unsigned size = load1->def.num_components * sizeof(bool);
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return memcmp(load1->value.b, load2->value.b, size) == 0;
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} else {
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unsigned size = load1->def.num_components * (load1->def.bit_size / 8);
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return memcmp(load1->value.f32, load2->value.f32, size) == 0;
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}
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}
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case nir_instr_type_phi: {
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nir_phi_instr *phi1 = nir_instr_as_phi(instr1);
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nir_phi_instr *phi2 = nir_instr_as_phi(instr2);
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if (phi1->instr.block != phi2->instr.block)
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return false;
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nir_foreach_phi_src(src1, phi1) {
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nir_foreach_phi_src(src2, phi2) {
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if (src1->pred == src2->pred) {
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if (!nir_srcs_equal(src1->src, src2->src))
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return false;
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break;
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}
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}
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}
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return true;
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}
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrinsic1 = nir_instr_as_intrinsic(instr1);
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nir_intrinsic_instr *intrinsic2 = nir_instr_as_intrinsic(instr2);
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const nir_intrinsic_info *info =
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&nir_intrinsic_infos[intrinsic1->intrinsic];
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if (intrinsic1->intrinsic != intrinsic2->intrinsic ||
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intrinsic1->num_components != intrinsic2->num_components)
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return false;
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if (info->has_dest && intrinsic1->dest.ssa.num_components !=
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intrinsic2->dest.ssa.num_components)
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return false;
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if (info->has_dest && intrinsic1->dest.ssa.bit_size !=
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intrinsic2->dest.ssa.bit_size)
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return false;
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for (unsigned i = 0; i < info->num_srcs; i++) {
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if (!nir_srcs_equal(intrinsic1->src[i], intrinsic2->src[i]))
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return false;
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}
|
|
|
|
for (unsigned i = 0; i < info->num_indices; i++) {
|
|
if (intrinsic1->const_index[i] != intrinsic2->const_index[i])
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
case nir_instr_type_call:
|
|
case nir_instr_type_jump:
|
|
case nir_instr_type_ssa_undef:
|
|
case nir_instr_type_parallel_copy:
|
|
default:
|
|
unreachable("Invalid instruction type");
|
|
}
|
|
|
|
unreachable("All cases in the above switch should return");
|
|
}
|
|
|
|
static bool
|
|
src_is_ssa(nir_src *src, void *data)
|
|
{
|
|
(void) data;
|
|
return src->is_ssa;
|
|
}
|
|
|
|
static bool
|
|
dest_is_ssa(nir_dest *dest, void *data)
|
|
{
|
|
(void) data;
|
|
return dest->is_ssa;
|
|
}
|
|
|
|
static inline bool
|
|
instr_each_src_and_dest_is_ssa(nir_instr *instr)
|
|
{
|
|
if (!nir_foreach_dest(instr, dest_is_ssa, NULL) ||
|
|
!nir_foreach_src(instr, src_is_ssa, NULL))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
/* This function determines if uses of an instruction can safely be rewritten
|
|
* to use another identical instruction instead. Note that this function must
|
|
* be kept in sync with hash_instr() and nir_instrs_equal() -- only
|
|
* instructions that pass this test will be handed on to those functions, and
|
|
* conversely they must handle everything that this function returns true for.
|
|
*/
|
|
|
|
static bool
|
|
instr_can_rewrite(nir_instr *instr)
|
|
{
|
|
/* We only handle SSA. */
|
|
assert(instr_each_src_and_dest_is_ssa(instr));
|
|
|
|
switch (instr->type) {
|
|
case nir_instr_type_alu:
|
|
case nir_instr_type_deref:
|
|
case nir_instr_type_tex:
|
|
case nir_instr_type_load_const:
|
|
case nir_instr_type_phi:
|
|
return true;
|
|
case nir_instr_type_intrinsic: {
|
|
const nir_intrinsic_info *info =
|
|
&nir_intrinsic_infos[nir_instr_as_intrinsic(instr)->intrinsic];
|
|
return (info->flags & NIR_INTRINSIC_CAN_ELIMINATE) &&
|
|
(info->flags & NIR_INTRINSIC_CAN_REORDER);
|
|
}
|
|
case nir_instr_type_call:
|
|
case nir_instr_type_jump:
|
|
case nir_instr_type_ssa_undef:
|
|
return false;
|
|
case nir_instr_type_parallel_copy:
|
|
default:
|
|
unreachable("Invalid instruction type");
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static nir_ssa_def *
|
|
nir_instr_get_dest_ssa_def(nir_instr *instr)
|
|
{
|
|
switch (instr->type) {
|
|
case nir_instr_type_alu:
|
|
assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
|
|
return &nir_instr_as_alu(instr)->dest.dest.ssa;
|
|
case nir_instr_type_deref:
|
|
assert(nir_instr_as_deref(instr)->dest.is_ssa);
|
|
return &nir_instr_as_deref(instr)->dest.ssa;
|
|
case nir_instr_type_load_const:
|
|
return &nir_instr_as_load_const(instr)->def;
|
|
case nir_instr_type_phi:
|
|
assert(nir_instr_as_phi(instr)->dest.is_ssa);
|
|
return &nir_instr_as_phi(instr)->dest.ssa;
|
|
case nir_instr_type_intrinsic:
|
|
assert(nir_instr_as_intrinsic(instr)->dest.is_ssa);
|
|
return &nir_instr_as_intrinsic(instr)->dest.ssa;
|
|
case nir_instr_type_tex:
|
|
assert(nir_instr_as_tex(instr)->dest.is_ssa);
|
|
return &nir_instr_as_tex(instr)->dest.ssa;
|
|
default:
|
|
unreachable("We never ask for any of these");
|
|
}
|
|
}
|
|
|
|
static bool
|
|
cmp_func(const void *data1, const void *data2)
|
|
{
|
|
return nir_instrs_equal(data1, data2);
|
|
}
|
|
|
|
struct set *
|
|
nir_instr_set_create(void *mem_ctx)
|
|
{
|
|
return _mesa_set_create(mem_ctx, hash_instr, cmp_func);
|
|
}
|
|
|
|
void
|
|
nir_instr_set_destroy(struct set *instr_set)
|
|
{
|
|
_mesa_set_destroy(instr_set, NULL);
|
|
}
|
|
|
|
bool
|
|
nir_instr_set_add_or_rewrite(struct set *instr_set, nir_instr *instr)
|
|
{
|
|
if (!instr_can_rewrite(instr))
|
|
return false;
|
|
|
|
uint32_t hash = hash_instr(instr);
|
|
struct set_entry *e = _mesa_set_search_pre_hashed(instr_set, hash, instr);
|
|
if (e) {
|
|
nir_ssa_def *def = nir_instr_get_dest_ssa_def(instr);
|
|
nir_instr *match = (nir_instr *) e->key;
|
|
nir_ssa_def *new_def = nir_instr_get_dest_ssa_def(match);
|
|
|
|
/* It's safe to replace an exact instruction with an inexact one as
|
|
* long as we make it exact. If we got here, the two instructions are
|
|
* exactly identical in every other way so, once we've set the exact
|
|
* bit, they are the same.
|
|
*/
|
|
if (instr->type == nir_instr_type_alu && nir_instr_as_alu(instr)->exact)
|
|
nir_instr_as_alu(match)->exact = true;
|
|
|
|
nir_ssa_def_rewrite_uses(def, nir_src_for_ssa(new_def));
|
|
return true;
|
|
}
|
|
|
|
_mesa_set_add_pre_hashed(instr_set, hash, instr);
|
|
return false;
|
|
}
|
|
|
|
void
|
|
nir_instr_set_remove(struct set *instr_set, nir_instr *instr)
|
|
{
|
|
if (!instr_can_rewrite(instr))
|
|
return;
|
|
|
|
struct set_entry *entry = _mesa_set_search(instr_set, instr);
|
|
if (entry)
|
|
_mesa_set_remove(instr_set, entry);
|
|
}
|
|
|