352 lines
9.7 KiB
C++
352 lines
9.7 KiB
C++
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include "util/ralloc.h"
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#include "brw_eu.h"
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#include <gtest/gtest.h>
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struct CompactParams {
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unsigned verx10;
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unsigned align;
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};
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std::string
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get_compact_params_name(const testing::TestParamInfo<CompactParams> p)
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{
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CompactParams params = p.param;
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std::stringstream ss;
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ss << params.verx10 << "_";
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switch (params.align) {
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case BRW_ALIGN_1:
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ss << "Align_1";
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break;
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case BRW_ALIGN_16:
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ss << "Align_16";
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break;
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default:
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unreachable("invalid align");
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}
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return ss.str();
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}
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static bool
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test_compact_instruction(struct brw_codegen *p, brw_inst src)
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{
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brw_compact_inst dst;
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memset(&dst, 0xd0, sizeof(dst));
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if (brw_try_compact_instruction(p->isa, &dst, &src)) {
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brw_inst uncompacted;
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brw_uncompact_instruction(p->isa, &uncompacted, &dst);
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if (memcmp(&uncompacted, &src, sizeof(src))) {
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brw_debug_compact_uncompact(p->isa, &src, &uncompacted);
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return false;
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}
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} else {
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brw_compact_inst unchanged;
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memset(&unchanged, 0xd0, sizeof(unchanged));
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/* It's not supposed to change dst unless it compacted. */
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if (memcmp(&unchanged, &dst, sizeof(dst))) {
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fprintf(stderr, "Failed to compact, but dst changed\n");
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fprintf(stderr, " Instruction: ");
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brw_disassemble_inst(stderr, p->isa, &src, false, 0, NULL);
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return false;
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}
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}
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return true;
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}
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/**
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* When doing fuzz testing, pad bits won't round-trip.
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*
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* This sort of a superset of skip_bit, which is testing for changing bits that
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* aren't worth testing for fuzzing. We also just want to clear bits that
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* become meaningless once fuzzing twiddles a related bit.
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*/
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static void
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clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst)
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
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brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
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brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
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brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
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brw_inst_set_bits(inst, 127, 111, 0);
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}
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if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV &&
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is_3src(isa, brw_inst_opcode(isa, inst))) {
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brw_inst_set_bits(inst, 105, 105, 0);
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brw_inst_set_bits(inst, 84, 84, 0);
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brw_inst_set_bits(inst, 36, 35, 0);
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}
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}
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static bool
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skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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/* pad bit */
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if (bit == 7)
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return true;
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/* The compact bit -- uncompacted can't have it set. */
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if (bit == 29)
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return true;
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if (is_3src(isa, brw_inst_opcode(isa, src))) {
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if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
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if (bit == 127)
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return true;
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} else {
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if (bit >= 126 && bit <= 127)
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return true;
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if (bit == 105)
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return true;
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if (bit == 84)
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return true;
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if (bit >= 35 && bit <= 36)
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return true;
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}
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} else {
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if (bit == 47)
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return true;
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if (devinfo->ver >= 8) {
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if (bit == 11)
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return true;
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if (bit == 95)
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return true;
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} else {
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if (devinfo->ver < 7 && bit == 90)
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return true;
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if (bit >= 91 && bit <= 95)
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return true;
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}
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}
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/* sometimes these are pad bits. */
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if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
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brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
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brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
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brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
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bit >= 121) {
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return true;
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}
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return false;
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}
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static bool
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test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
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{
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for (int bit0 = 0; bit0 < 128; bit0++) {
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if (skip_bit(p->isa, &src, bit0))
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continue;
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for (int bit1 = 0; bit1 < 128; bit1++) {
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brw_inst instr = src;
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uint64_t *bits = instr.data;
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if (skip_bit(p->isa, &src, bit1))
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continue;
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bits[bit0 / 64] ^= (1ull << (bit0 & 63));
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bits[bit1 / 64] ^= (1ull << (bit1 & 63));
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clear_pad_bits(p->isa, &instr);
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if (!brw_validate_instruction(p->isa, &instr, 0, sizeof(brw_inst), NULL))
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continue;
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if (!test_compact_instruction(p, instr)) {
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printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1);
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return false;
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}
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}
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}
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return true;
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}
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class CompactTestFixture : public testing::TestWithParam<CompactParams> {
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protected:
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virtual void SetUp() {
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CompactParams params = GetParam();
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mem_ctx = ralloc_context(NULL);
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devinfo = rzalloc(mem_ctx, intel_device_info);
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p = rzalloc(mem_ctx, brw_codegen);
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devinfo->verx10 = params.verx10;
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devinfo->ver = devinfo->verx10 / 10;
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brw_init_isa_info(&isa, devinfo);
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brw_init_codegen(&isa, p, p);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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brw_set_default_access_mode(p, params.align);
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};
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virtual void TearDown() {
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EXPECT_EQ(p->nr_insn, 1);
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EXPECT_TRUE(test_compact_instruction(p, p->store[0]));
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EXPECT_TRUE(test_fuzz_compact_instruction(p, p->store[0]));
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ralloc_free(mem_ctx);
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};
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void *mem_ctx;
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struct brw_isa_info isa;
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intel_device_info *devinfo;
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brw_codegen *p;
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};
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class Instructions : public CompactTestFixture {};
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INSTANTIATE_TEST_CASE_P(
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CompactTest,
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Instructions,
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testing::Values(
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CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
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CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 },
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CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 },
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CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 },
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CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 },
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CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 },
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CompactParams{ 110, BRW_ALIGN_1 },
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CompactParams{ 120, BRW_ALIGN_1 },
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CompactParams{ 125, BRW_ALIGN_1 }
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),
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get_compact_params_name);
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class InstructionsBeforeIvyBridge : public CompactTestFixture {};
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INSTANTIATE_TEST_CASE_P(
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CompactTest,
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InstructionsBeforeIvyBridge,
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testing::Values(
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CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
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CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 }
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),
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get_compact_params_name);
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TEST_P(Instructions, ADD_GRF_GRF_GRF)
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{
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struct brw_reg g0 = brw_vec8_grf(0, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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struct brw_reg g4 = brw_vec8_grf(4, 0);
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brw_ADD(p, g0, g2, g4);
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}
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TEST_P(Instructions, ADD_GRF_GRF_IMM)
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{
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struct brw_reg g0 = brw_vec8_grf(0, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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brw_ADD(p, g0, g2, brw_imm_f(1.0));
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}
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TEST_P(Instructions, ADD_GRF_GRF_IMM_d)
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{
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struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
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struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
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brw_ADD(p, g0, g2, brw_imm_d(1));
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}
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TEST_P(Instructions, MOV_GRF_GRF)
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{
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struct brw_reg g0 = brw_vec8_grf(0, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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brw_MOV(p, g0, g2);
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}
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TEST_P(InstructionsBeforeIvyBridge, ADD_MRF_GRF_GRF)
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{
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struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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struct brw_reg g4 = brw_vec8_grf(4, 0);
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brw_ADD(p, m6, g2, g4);
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}
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TEST_P(Instructions, ADD_vec1_GRF_GRF_GRF)
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{
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struct brw_reg g0 = brw_vec1_grf(0, 0);
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struct brw_reg g2 = brw_vec1_grf(2, 0);
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struct brw_reg g4 = brw_vec1_grf(4, 0);
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brw_ADD(p, g0, g2, g4);
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}
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TEST_P(InstructionsBeforeIvyBridge, PLN_MRF_GRF_GRF)
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{
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struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
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struct brw_reg interp = brw_vec1_grf(2, 0);
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struct brw_reg g4 = brw_vec8_grf(4, 0);
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brw_PLN(p, m6, interp, g4);
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}
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TEST_P(Instructions, f0_0_MOV_GRF_GRF)
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{
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struct brw_reg g0 = brw_vec8_grf(0, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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brw_push_insn_state(p);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
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brw_MOV(p, g0, g2);
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brw_pop_insn_state(p);
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}
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/* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test
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* it, so that we run the fuzzing can run over all the other bits that might
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* interact with it.
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*/
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TEST_P(Instructions, f0_1_MOV_GRF_GRF)
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{
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struct brw_reg g0 = brw_vec8_grf(0, 0);
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struct brw_reg g2 = brw_vec8_grf(2, 0);
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brw_push_insn_state(p);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
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brw_inst *mov = brw_MOV(p, g0, g2);
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brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
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brw_pop_insn_state(p);
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}
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