mesa/src/intel
Kenneth Graunke 82ee30e558 intel/eu: Handle compaction when inserting validation errors
When the EU validator encountered an error, it would add an annotation
to the disassembly.  Unfortunately, the code to insert an error assumed
that the next instruction would start at (offset + sizeof(brw_inst)),
which is not true if the instruction with an error is compacted.

This could lead to cascading disassembly errors, where we started trying
to decode the next instruction at the wrong offset, and getting lots of
scary looking output:

   ERROR: Register Regioning patterns where [...]
   (-f0.1.any16h) illegal(*** invalid execution size value 6 )      { align1 $7.src atomic };
   (+f0.1.any16h) illegal.sat(*** invalid execution size value 6 )  { align1 $9.src AccWrEnable };
   illegal(*** invalid execution size value 6 )                     { align1 $11.src };
   (+f0.1) illegal.sat(*** invalid execution size value 6 )         { align1 F@2 AccWrEnable };
   (+f0.1) illegal.sat(*** invalid execution size value 6 )         { align1 F@2 AccWrEnable };
   (+f0.1) illegal.sat(*** invalid execution size value 6 )         { align1 $15.src AccWrEnable };
   illegal(*** invalid execution size value 6 )                     { align1 $15.src };
   (+f0.1) illegal.sat.g.f0.1(*** invalid execution size value 6 )  { align1 $13.src AccWrEnable };

Only the first instruction was actually wrong - the rest are just a
result of starting the disassembler at the wrong offset.  Trash ensues!

To fix this, just pass the instruction size in a few layers so we can
record the next offset properly.

Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17624>
2022-07-28 21:31:45 +00:00
..
blorp intel/blorp: Set uses_sample_shading for MSAA blit shaders 2022-07-13 20:28:42 +00:00
ci intel/fs: Use nir_lower_single_sampled 2022-07-13 20:28:42 +00:00
common intel: protect against empty invalidate ranges 2022-07-13 01:33:27 +00:00
compiler intel/eu: Handle compaction when inserting validation errors 2022-07-28 21:31:45 +00:00
dev intel/dev: Determine the amount of free vram using small BAR uapi 2022-07-26 20:34:02 +00:00
ds u_trace/anv/iris: drop cs argument for recording traces 2022-05-19 19:04:28 +00:00
genxml intel: fix typos found by codespell 2022-06-27 10:20:55 +00:00
isl isl: add new helper for format component compatibility 2022-07-11 14:57:26 +00:00
nullhw-layer vulkan: drop empty vulkan_wsi_args 2022-04-27 11:51:26 +00:00
perf intel: fix typos found by codespell 2022-06-27 10:20:55 +00:00
tools intel/compiler: Introduce a new brw_isa_info structure 2022-06-30 23:46:35 +00:00
vulkan util/list: rename LIST_ENTRY() to list_entry() 2022-07-28 10:10:44 +00:00
meson.build anv: add perfetto source 2022-01-14 20:17:44 +00:00