207 lines
6.8 KiB
C
207 lines
6.8 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_cfg.h"
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#include "brw_eu.h"
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#include "brw_disasm_info.h"
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#include "dev/intel_debug.h"
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#include "compiler/nir/nir.h"
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__attribute__((weak)) void nir_print_instr(UNUSED const nir_instr *instr,
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UNUSED FILE *fp) {}
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void
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dump_assembly(void *assembly, int start_offset, int end_offset,
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struct disasm_info *disasm, const unsigned *block_latency)
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{
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const struct brw_isa_info *isa = disasm->isa;
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const char *last_annotation_string = NULL;
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const void *last_annotation_ir = NULL;
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void *mem_ctx = ralloc_context(NULL);
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const struct brw_label *root_label =
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brw_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx);
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foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
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struct exec_node *next_node = exec_node_get_next(&group->link);
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if (exec_node_is_tail_sentinel(next_node))
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break;
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struct inst_group *next =
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exec_node_data(struct inst_group, next_node, link);
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int start_offset = group->offset;
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int end_offset = next->offset;
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if (group->block_start) {
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fprintf(stderr, " START B%d", group->block_start->num);
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foreach_list_typed(struct bblock_link, predecessor_link, link,
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&group->block_start->parents) {
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struct bblock_t *predecessor_block = predecessor_link->block;
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fprintf(stderr, " <-B%d", predecessor_block->num);
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}
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if (block_latency)
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fprintf(stderr, " (%u cycles)",
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block_latency[group->block_start->num]);
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fprintf(stderr, "\n");
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}
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if (last_annotation_ir != group->ir) {
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last_annotation_ir = group->ir;
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if (last_annotation_ir) {
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fprintf(stderr, " ");
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nir_print_instr(group->ir, stderr);
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fprintf(stderr, "\n");
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}
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}
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if (last_annotation_string != group->annotation) {
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last_annotation_string = group->annotation;
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if (last_annotation_string)
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fprintf(stderr, " %s\n", last_annotation_string);
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}
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brw_disassemble(isa, assembly, start_offset, end_offset,
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root_label, stderr);
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if (group->error) {
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fputs(group->error, stderr);
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}
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if (group->block_end) {
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fprintf(stderr, " END B%d", group->block_end->num);
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foreach_list_typed(struct bblock_link, successor_link, link,
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&group->block_end->children) {
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struct bblock_t *successor_block = successor_link->block;
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fprintf(stderr, " ->B%d", successor_block->num);
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}
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fprintf(stderr, "\n");
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}
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}
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fprintf(stderr, "\n");
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ralloc_free(mem_ctx);
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}
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struct disasm_info *
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disasm_initialize(const struct brw_isa_info *isa,
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const struct cfg_t *cfg)
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{
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struct disasm_info *disasm = ralloc(NULL, struct disasm_info);
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exec_list_make_empty(&disasm->group_list);
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disasm->isa = isa;
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disasm->cfg = cfg;
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disasm->cur_block = 0;
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disasm->use_tail = false;
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return disasm;
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}
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struct inst_group *
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disasm_new_inst_group(struct disasm_info *disasm, unsigned next_inst_offset)
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{
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struct inst_group *tail = rzalloc(disasm, struct inst_group);
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tail->offset = next_inst_offset;
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exec_list_push_tail(&disasm->group_list, &tail->link);
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return tail;
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}
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void
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disasm_annotate(struct disasm_info *disasm,
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struct backend_instruction *inst, unsigned offset)
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{
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const struct intel_device_info *devinfo = disasm->isa->devinfo;
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const struct cfg_t *cfg = disasm->cfg;
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struct inst_group *group;
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if (!disasm->use_tail) {
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group = disasm_new_inst_group(disasm, offset);
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} else {
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disasm->use_tail = false;
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group = exec_node_data(struct inst_group,
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exec_list_get_tail_raw(&disasm->group_list), link);
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}
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if (INTEL_DEBUG(DEBUG_ANNOTATION)) {
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group->ir = inst->ir;
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group->annotation = inst->annotation;
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}
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if (bblock_start(cfg->blocks[disasm->cur_block]) == inst) {
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group->block_start = cfg->blocks[disasm->cur_block];
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}
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/* There is no hardware DO instruction on Gfx6+, so since DO always
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* starts a basic block, we need to set the .block_start of the next
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* instruction's annotation with a pointer to the bblock started by
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* the DO.
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*
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* There's also only complication from emitting an annotation without
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* a corresponding hardware instruction to disassemble.
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*/
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if (devinfo->ver >= 6 && inst->opcode == BRW_OPCODE_DO) {
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disasm->use_tail = true;
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}
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if (bblock_end(cfg->blocks[disasm->cur_block]) == inst) {
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group->block_end = cfg->blocks[disasm->cur_block];
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disasm->cur_block++;
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}
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}
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void
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disasm_insert_error(struct disasm_info *disasm, unsigned offset,
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unsigned inst_size, const char *error)
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{
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foreach_list_typed(struct inst_group, cur, link, &disasm->group_list) {
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struct exec_node *next_node = exec_node_get_next(&cur->link);
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if (exec_node_is_tail_sentinel(next_node))
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break;
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struct inst_group *next =
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exec_node_data(struct inst_group, next_node, link);
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if (next->offset <= offset)
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continue;
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if (offset + inst_size != next->offset) {
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struct inst_group *new = ralloc(disasm, struct inst_group);
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memcpy(new, cur, sizeof(struct inst_group));
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cur->error = NULL;
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cur->error_length = 0;
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cur->block_end = NULL;
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new->offset = offset + inst_size;
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new->block_start = NULL;
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exec_node_insert_after(&cur->link, &new->link);
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}
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if (cur->error)
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ralloc_strcat(&cur->error, error);
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else
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cur->error = ralloc_strdup(disasm, error);
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return;
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}
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}
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