526 lines
17 KiB
C
526 lines
17 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jason Ekstrand (jason@jlekstrand.net)
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*
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*/
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#include "nir.h"
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#include "nir/nir_builder.h"
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#include "nir_control_flow.h"
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#include "nir_search_helpers.h"
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/*
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* Implements a small peephole optimization that looks for
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*
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* if (cond) {
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* <then SSA defs>
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* } else {
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* <else SSA defs>
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* }
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* phi
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* ...
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* phi
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*
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* and replaces it with:
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*
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* <then SSA defs>
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* <else SSA defs>
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* bcsel
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* ...
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* bcsel
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*
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* where the SSA defs are ALU operations or other cheap instructions (not
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* texturing, for example).
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*
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* If the number of ALU operations in the branches is greater than the limit
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* parameter, then the optimization is skipped. In limit=0 mode, the SSA defs
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* must only be MOVs which we expect to get copy-propagated away once they're
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* out of the inner blocks.
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*/
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static bool
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block_check_for_allowed_instrs(nir_block *block, unsigned *count,
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unsigned limit, bool indirect_load_ok,
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bool expensive_alu_ok)
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{
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bool alu_ok = limit != 0;
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/* Used on non-control-flow HW to flatten all IFs. */
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if (limit == ~0) {
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nir_foreach_instr(instr, block) {
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switch (instr->type) {
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case nir_instr_type_alu:
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case nir_instr_type_deref:
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case nir_instr_type_load_const:
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case nir_instr_type_phi:
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case nir_instr_type_ssa_undef:
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case nir_instr_type_tex:
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break;
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case nir_instr_type_intrinsic:
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if (!nir_intrinsic_can_reorder(nir_instr_as_intrinsic(instr)))
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return false;
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break;
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case nir_instr_type_call:
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case nir_instr_type_jump:
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case nir_instr_type_parallel_copy:
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return false;
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}
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}
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return true;
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}
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nir_foreach_instr(instr, block) {
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_deref: {
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nir_deref_instr *const deref = nir_src_as_deref(intrin->src[0]);
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switch (deref->modes) {
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case nir_var_shader_in:
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case nir_var_uniform:
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case nir_var_image:
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/* Don't try to remove flow control around an indirect load
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* because that flow control may be trying to avoid invalid
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* loads.
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*/
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if (!indirect_load_ok && nir_deref_instr_has_indirect(deref))
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return false;
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break;
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default:
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return false;
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}
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break;
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}
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case nir_intrinsic_load_uniform:
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case nir_intrinsic_load_helper_invocation:
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case nir_intrinsic_is_helper_invocation:
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case nir_intrinsic_load_front_face:
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case nir_intrinsic_load_view_index:
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case nir_intrinsic_load_layer_id:
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case nir_intrinsic_load_frag_coord:
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case nir_intrinsic_load_sample_pos:
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case nir_intrinsic_load_sample_pos_or_center:
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case nir_intrinsic_load_sample_id:
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case nir_intrinsic_load_sample_mask_in:
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case nir_intrinsic_load_vertex_id_zero_base:
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case nir_intrinsic_load_first_vertex:
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case nir_intrinsic_load_base_instance:
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case nir_intrinsic_load_instance_id:
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case nir_intrinsic_load_draw_id:
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case nir_intrinsic_load_num_workgroups:
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case nir_intrinsic_load_workgroup_id:
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case nir_intrinsic_load_local_invocation_id:
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case nir_intrinsic_load_local_invocation_index:
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case nir_intrinsic_load_subgroup_id:
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case nir_intrinsic_load_subgroup_invocation:
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case nir_intrinsic_load_num_subgroups:
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case nir_intrinsic_load_frag_shading_rate:
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case nir_intrinsic_is_sparse_texels_resident:
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case nir_intrinsic_sparse_residency_code_and:
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if (!alu_ok)
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return false;
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break;
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default:
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return false;
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}
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break;
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}
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case nir_instr_type_deref:
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case nir_instr_type_load_const:
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case nir_instr_type_ssa_undef:
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break;
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case nir_instr_type_alu: {
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nir_alu_instr *mov = nir_instr_as_alu(instr);
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bool movelike = false;
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switch (mov->op) {
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case nir_op_mov:
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case nir_op_fneg:
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case nir_op_ineg:
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case nir_op_fabs:
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case nir_op_iabs:
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case nir_op_vec2:
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case nir_op_vec3:
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case nir_op_vec4:
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case nir_op_vec5:
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case nir_op_vec8:
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case nir_op_vec16:
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movelike = true;
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break;
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case nir_op_fcos:
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case nir_op_fdiv:
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case nir_op_fexp2:
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case nir_op_flog2:
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case nir_op_fmod:
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case nir_op_fpow:
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case nir_op_frcp:
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case nir_op_frem:
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case nir_op_frsq:
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case nir_op_fsin:
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case nir_op_idiv:
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case nir_op_irem:
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case nir_op_udiv:
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if (!alu_ok || !expensive_alu_ok)
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return false;
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break;
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default:
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if (!alu_ok) {
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/* It must be a move-like operation. */
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return false;
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}
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break;
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}
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/* It must be SSA */
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if (!mov->dest.dest.is_ssa)
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return false;
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if (alu_ok) {
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/* If the ALU operation is an fsat or a move-like operation, do
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* not count it. The expectation is that it will eventually be
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* merged as a destination modifier or source modifier on some
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* other instruction.
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*/
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if (mov->op != nir_op_fsat && !movelike)
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(*count)++;
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} else {
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/* Can't handle saturate */
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if (mov->dest.saturate)
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return false;
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/* It cannot have any if-uses */
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if (!list_is_empty(&mov->dest.dest.ssa.if_uses))
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return false;
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/* The only uses of this definition must be phis in the successor */
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nir_foreach_use(use, &mov->dest.dest.ssa) {
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if (use->parent_instr->type != nir_instr_type_phi ||
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use->parent_instr->block != block->successors[0])
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return false;
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}
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}
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break;
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}
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default:
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return false;
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}
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}
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return true;
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}
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/**
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* Try to collapse nested ifs:
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* This optimization turns
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*
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* if (cond1) {
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* <allowed instruction>
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* if (cond2) {
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* <any code>
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* } else {
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* }
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* } else {
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* }
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*
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* into
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*
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* <allowed instruction>
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* if (cond1 && cond2) {
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* <any code>
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* } else {
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* }
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*
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*/
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static bool
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nir_opt_collapse_if(nir_if *if_stmt, nir_shader *shader, unsigned limit,
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bool indirect_load_ok, bool expensive_alu_ok)
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{
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/* the if has to be nested */
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if (if_stmt->cf_node.parent->type != nir_cf_node_if)
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return false;
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nir_if *parent_if = nir_cf_node_as_if(if_stmt->cf_node.parent);
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if (parent_if->control == nir_selection_control_dont_flatten)
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return false;
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/* check if the else block is empty */
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if (!nir_cf_list_is_empty_block(&if_stmt->else_list))
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return false;
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/* this opt doesn't make much sense if the branch is empty */
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if (nir_cf_list_is_empty_block(&if_stmt->then_list))
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return false;
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/* the nested if has to be the only cf_node:
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* i.e. <block> <if_stmt> <block> */
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if (exec_list_length(&parent_if->then_list) != 3)
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return false;
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/* check if the else block of the parent if is empty */
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if (!nir_cf_list_is_empty_block(&parent_if->else_list))
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return false;
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/* check if the block after the nested if is empty except for phis */
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nir_block *last = nir_if_last_then_block(parent_if);
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nir_instr *last_instr = nir_block_last_instr(last);
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if (last_instr && last_instr->type != nir_instr_type_phi)
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return false;
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/* check if all outer phis become trivial after merging the ifs */
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nir_foreach_instr(instr, last) {
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if (parent_if->control == nir_selection_control_flatten)
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break;
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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nir_phi_src *else_src =
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nir_phi_get_src_from_block(phi, nir_if_first_else_block(if_stmt));
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nir_foreach_use (src, &phi->dest.ssa) {
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assert(src->parent_instr->type == nir_instr_type_phi);
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nir_phi_src *phi_src =
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nir_phi_get_src_from_block(nir_instr_as_phi(src->parent_instr),
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nir_if_first_else_block(parent_if));
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if (phi_src->src.ssa != else_src->src.ssa)
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return false;
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}
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}
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if (parent_if->control == nir_selection_control_flatten) {
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/* Override driver defaults */
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indirect_load_ok = true;
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expensive_alu_ok = true;
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}
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/* check if the block before the nested if matches the requirements */
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nir_block *first = nir_if_first_then_block(parent_if);
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unsigned count = 0;
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if (!block_check_for_allowed_instrs(first, &count, limit != 0,
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indirect_load_ok, expensive_alu_ok))
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return false;
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if (count > limit && parent_if->control != nir_selection_control_flatten)
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return false;
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/* trivialize succeeding phis */
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nir_foreach_instr(instr, last) {
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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nir_phi_src *else_src =
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nir_phi_get_src_from_block(phi, nir_if_first_else_block(if_stmt));
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nir_foreach_use_safe(src, &phi->dest.ssa) {
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nir_phi_src *phi_src =
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nir_phi_get_src_from_block(nir_instr_as_phi(src->parent_instr),
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nir_if_first_else_block(parent_if));
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if (phi_src->src.ssa == else_src->src.ssa)
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nir_instr_rewrite_src(src->parent_instr, &phi_src->src,
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nir_src_for_ssa(&phi->dest.ssa));
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}
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}
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/* combine the conditions */
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struct nir_builder b;
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nir_builder_init(&b, nir_cf_node_get_function(&if_stmt->cf_node)->function->impl);
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b.cursor = nir_before_cf_node(&if_stmt->cf_node);
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nir_ssa_def *cond = nir_iand(&b, if_stmt->condition.ssa,
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parent_if->condition.ssa);
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nir_if_rewrite_condition(if_stmt, nir_src_for_ssa(cond));
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/* move the whole inner if before the parent if */
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nir_cf_list tmp;
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nir_cf_extract(&tmp, nir_before_block(first),
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nir_after_block(last));
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nir_cf_reinsert(&tmp, nir_before_cf_node(&parent_if->cf_node));
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/* The now empty parent if will be cleaned up by other passes */
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return true;
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}
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static bool
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nir_opt_peephole_select_block(nir_block *block, nir_shader *shader,
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unsigned limit, bool indirect_load_ok,
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bool expensive_alu_ok)
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{
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if (nir_cf_node_is_first(&block->cf_node))
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return false;
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nir_cf_node *prev_node = nir_cf_node_prev(&block->cf_node);
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if (prev_node->type != nir_cf_node_if)
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return false;
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nir_block *prev_block = nir_cf_node_as_block(nir_cf_node_prev(prev_node));
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/* If the last instruction before this if/else block is a jump, we can't
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* append stuff after it because it would break a bunch of assumption about
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* control flow (nir_validate expects the successor of a return/halt jump
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* to be the end of the function, which might not match the successor of
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* the if/else blocks).
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*/
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if (nir_block_ends_in_return_or_halt(prev_block))
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return false;
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nir_if *if_stmt = nir_cf_node_as_if(prev_node);
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/* first, try to collapse the if */
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if (nir_opt_collapse_if(if_stmt, shader, limit,
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indirect_load_ok, expensive_alu_ok))
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return true;
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if (if_stmt->control == nir_selection_control_dont_flatten)
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return false;
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nir_block *then_block = nir_if_first_then_block(if_stmt);
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nir_block *else_block = nir_if_first_else_block(if_stmt);
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/* We can only have one block in each side ... */
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if (nir_if_last_then_block(if_stmt) != then_block ||
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nir_if_last_else_block(if_stmt) != else_block)
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return false;
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if (if_stmt->control == nir_selection_control_flatten) {
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/* Override driver defaults */
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indirect_load_ok = true;
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expensive_alu_ok = true;
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}
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/* ... and those blocks must only contain "allowed" instructions. */
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unsigned count = 0;
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if (!block_check_for_allowed_instrs(then_block, &count, limit,
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indirect_load_ok, expensive_alu_ok) ||
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!block_check_for_allowed_instrs(else_block, &count, limit,
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indirect_load_ok, expensive_alu_ok))
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return false;
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if (count > limit && if_stmt->control != nir_selection_control_flatten)
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return false;
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/* At this point, we know that the previous CFG node is an if-then
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* statement containing only moves to phi nodes in this block. We can
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* just remove that entire CF node and replace all of the phi nodes with
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* selects.
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*/
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/* First, we move the remaining instructions from the blocks to the
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* block before. We have already guaranteed that this is safe by
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* calling block_check_for_allowed_instrs()
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*/
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nir_foreach_instr_safe(instr, then_block) {
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exec_node_remove(&instr->node);
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instr->block = prev_block;
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exec_list_push_tail(&prev_block->instr_list, &instr->node);
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}
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nir_foreach_instr_safe(instr, else_block) {
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exec_node_remove(&instr->node);
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instr->block = prev_block;
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exec_list_push_tail(&prev_block->instr_list, &instr->node);
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}
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_phi)
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break;
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel);
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nir_src_copy(&sel->src[0].src, &if_stmt->condition);
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/* Splat the condition to all channels */
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memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
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assert(exec_list_length(&phi->srcs) == 2);
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nir_foreach_phi_src(src, phi) {
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assert(src->pred == then_block || src->pred == else_block);
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assert(src->src.is_ssa);
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unsigned idx = src->pred == then_block ? 1 : 2;
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nir_src_copy(&sel->src[idx].src, &src->src);
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}
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nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
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phi->dest.ssa.num_components,
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phi->dest.ssa.bit_size, NULL);
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sel->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
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nir_ssa_def_rewrite_uses(&phi->dest.ssa,
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&sel->dest.dest.ssa);
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nir_instr_insert_before(&phi->instr, &sel->instr);
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nir_instr_remove(&phi->instr);
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}
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nir_cf_node_remove(&if_stmt->cf_node);
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return true;
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}
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static bool
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nir_opt_peephole_select_impl(nir_function_impl *impl, unsigned limit,
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bool indirect_load_ok, bool expensive_alu_ok)
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{
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nir_shader *shader = impl->function->shader;
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bool progress = false;
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nir_foreach_block_safe(block, impl) {
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progress |= nir_opt_peephole_select_block(block, shader, limit,
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indirect_load_ok,
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expensive_alu_ok);
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}
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if (progress) {
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nir_metadata_preserve(impl, nir_metadata_none);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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return progress;
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}
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bool
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nir_opt_peephole_select(nir_shader *shader, unsigned limit,
|
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bool indirect_load_ok, bool expensive_alu_ok)
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|
{
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bool progress = false;
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|
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nir_foreach_function(function, shader) {
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if (function->impl)
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progress |= nir_opt_peephole_select_impl(function->impl, limit,
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indirect_load_ok,
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|
expensive_alu_ok);
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}
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|
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return progress;
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}
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