214 lines
6.7 KiB
C
214 lines
6.7 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jason Ekstrand (jason@jlekstrand.net)
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*
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*/
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#include "nir.h"
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/*
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* Implements a pass that tries to move uses vecN sources to their
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* destinations. This is kind of like an inverse copy-propagation pass.
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* For instance, if you have
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*
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* ssa_1 = vec4(a, b, c, d)
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* ssa_2 = fadd(a, b)
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*
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* This will be turned into
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*
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* ssa_1 = vec4(a, b, c, d)
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* ssa_2 = fadd(ssa_1.x, ssa_1.y)
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*
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* While this is "worse" because it adds a bunch of unneeded dependencies, it
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* actually makes it much easier for vec4-based backends to coalesce the MOVs
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* that result from the vec4 operation because it doesn't have to worry about
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* quite as many reads.
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*/
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/* Returns true if the given SSA def dominates the instruction. An SSA def is
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* considered to *not* dominate the instruction that defines it.
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*/
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static bool
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ssa_def_dominates_instr(nir_ssa_def *def, nir_instr *instr)
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{
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if (instr->index <= def->parent_instr->index) {
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return false;
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} else if (def->parent_instr->block == instr->block) {
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return def->parent_instr->index < instr->index;
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} else {
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return nir_block_dominates(def->parent_instr->block, instr->block);
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}
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}
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static bool
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move_vec_src_uses_to_dest_block(nir_block *block)
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{
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bool progress = false;
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_alu)
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continue;
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nir_alu_instr *vec = nir_instr_as_alu(instr);
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switch (vec->op) {
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case nir_op_vec2:
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case nir_op_vec3:
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case nir_op_vec4:
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break;
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default:
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continue; /* The loop */
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}
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/* Can't handle non-SSA vec operations */
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if (!vec->dest.dest.is_ssa)
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continue;
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/* Can't handle saturation */
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if (vec->dest.saturate)
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continue;
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/* First, mark all of the sources we are going to consider for rewriting
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* to the destination
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*/
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int srcs_remaining = 0;
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for (unsigned i = 0; i < nir_op_infos[vec->op].num_inputs; i++) {
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/* We can't rewrite a source if it's not in SSA form */
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if (!vec->src[i].src.is_ssa)
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continue;
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/* We can't rewrite a source if it has modifiers */
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if (vec->src[i].abs || vec->src[i].negate)
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continue;
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srcs_remaining |= 1 << i;
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}
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/* We can't actually do anything with this instruction */
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if (srcs_remaining == 0)
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continue;
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for (unsigned i; i = ffs(srcs_remaining) - 1, srcs_remaining;) {
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int8_t swizzle[NIR_MAX_VEC_COMPONENTS];
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memset(swizzle, -1, sizeof(swizzle));
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for (unsigned j = i; j < nir_op_infos[vec->op].num_inputs; j++) {
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if (vec->src[j].src.ssa != vec->src[i].src.ssa)
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continue;
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/* Mark the given channel as having been handled */
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srcs_remaining &= ~(1 << j);
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/* Mark the appropriate channel as coming from src j */
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swizzle[vec->src[j].swizzle[0]] = j;
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}
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nir_foreach_use_safe(use, vec->src[i].src.ssa) {
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if (use->parent_instr == &vec->instr)
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continue;
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/* We need to dominate the use if we are going to rewrite it */
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if (!ssa_def_dominates_instr(&vec->dest.dest.ssa, use->parent_instr))
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continue;
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/* For now, we'll just rewrite ALU instructions */
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if (use->parent_instr->type != nir_instr_type_alu)
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continue;
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assert(use->is_ssa);
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nir_alu_instr *use_alu = nir_instr_as_alu(use->parent_instr);
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/* Figure out which source we're actually looking at */
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nir_alu_src *use_alu_src = exec_node_data(nir_alu_src, use, src);
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unsigned src_idx = use_alu_src - use_alu->src;
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assert(src_idx < nir_op_infos[use_alu->op].num_inputs);
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bool can_reswizzle = true;
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for (unsigned j = 0; j < 4; j++) {
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if (!nir_alu_instr_channel_used(use_alu, src_idx, j))
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continue;
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if (swizzle[use_alu_src->swizzle[j]] == -1) {
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can_reswizzle = false;
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break;
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}
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}
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if (!can_reswizzle)
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continue;
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/* At this point, we have determined that the given use can be
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* reswizzled to actually use the destination of the vecN operation.
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* Go ahead and rewrite it as needed.
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*/
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nir_instr_rewrite_src(use->parent_instr, use,
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nir_src_for_ssa(&vec->dest.dest.ssa));
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for (unsigned j = 0; j < 4; j++) {
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if (!nir_alu_instr_channel_used(use_alu, src_idx, j))
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continue;
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use_alu_src->swizzle[j] = swizzle[use_alu_src->swizzle[j]];
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progress = true;
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}
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}
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}
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}
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return progress;
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}
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static bool
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nir_move_vec_src_uses_to_dest_impl(nir_shader *shader, nir_function_impl *impl)
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{
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bool progress = false;
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nir_metadata_require(impl, nir_metadata_dominance);
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nir_index_instrs(impl);
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nir_foreach_block(block, impl) {
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progress |= move_vec_src_uses_to_dest_block(block);
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}
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nir_metadata_preserve(impl, nir_metadata_block_index |
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nir_metadata_dominance);
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return progress;
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}
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bool
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nir_move_vec_src_uses_to_dest(nir_shader *shader)
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{
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bool progress = false;
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nir_foreach_function(function, shader) {
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if (function->impl)
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progress |= nir_move_vec_src_uses_to_dest_impl(shader,
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function->impl);
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}
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return progress;
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}
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