291 lines
9.4 KiB
C
291 lines
9.4 KiB
C
/*
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* Copyright © 2015 Red Hat
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/* Has two paths
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* One (nir_lower_idiv_fast) lowers idiv/udiv/umod and is based on
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* NV50LegalizeSSA::handleDIV()
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*
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* Note that this path probably does not have not enough precision for
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* compute shaders. Perhaps we want a second higher precision (looping)
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* version of this? Or perhaps we assume if you can do compute shaders you
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* can also branch out to a pre-optimized shader library routine..
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*
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* The other path (nir_lower_idiv_precise) is based off of code used by LLVM's
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* AMDGPU target. It should handle 32-bit idiv/irem/imod/udiv/umod exactly.
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*/
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static nir_ssa_def *
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convert_instr(nir_builder *bld, nir_op op,
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nir_ssa_def *numer, nir_ssa_def *denom)
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{
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nir_ssa_def *af, *bf, *a, *b, *q, *r, *rt;
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bool is_signed;
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is_signed = (op == nir_op_idiv ||
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op == nir_op_imod ||
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op == nir_op_irem);
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if (is_signed) {
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af = nir_i2f32(bld, numer);
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bf = nir_i2f32(bld, denom);
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af = nir_fabs(bld, af);
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bf = nir_fabs(bld, bf);
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a = nir_iabs(bld, numer);
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b = nir_iabs(bld, denom);
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} else {
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af = nir_u2f32(bld, numer);
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bf = nir_u2f32(bld, denom);
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a = numer;
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b = denom;
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}
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/* get first result: */
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bf = nir_frcp(bld, bf);
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bf = nir_isub(bld, bf, nir_imm_int(bld, 2)); /* yes, really */
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q = nir_fmul(bld, af, bf);
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if (is_signed) {
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q = nir_f2i32(bld, q);
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} else {
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q = nir_f2u32(bld, q);
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}
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/* get error of first result: */
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r = nir_imul(bld, q, b);
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r = nir_isub(bld, a, r);
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r = nir_u2f32(bld, r);
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r = nir_fmul(bld, r, bf);
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r = nir_f2u32(bld, r);
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/* add quotients: */
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q = nir_iadd(bld, q, r);
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/* correction: if modulus >= divisor, add 1 */
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r = nir_imul(bld, q, b);
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r = nir_isub(bld, a, r);
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rt = nir_uge(bld, r, b);
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if (op == nir_op_umod) {
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q = nir_bcsel(bld, rt, nir_isub(bld, r, b), r);
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} else {
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r = nir_b2i32(bld, rt);
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q = nir_iadd(bld, q, r);
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if (is_signed) {
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/* fix the sign: */
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r = nir_ixor(bld, numer, denom);
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r = nir_ilt(bld, r, nir_imm_int(bld, 0));
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b = nir_ineg(bld, q);
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q = nir_bcsel(bld, r, b, q);
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if (op == nir_op_imod || op == nir_op_irem) {
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q = nir_imul(bld, q, denom);
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q = nir_isub(bld, numer, q);
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if (op == nir_op_imod) {
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q = nir_bcsel(bld, nir_ieq_imm(bld, q, 0),
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nir_imm_int(bld, 0),
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nir_bcsel(bld, r, nir_iadd(bld, q, denom), q));
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}
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}
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}
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}
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return q;
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}
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/* ported from LLVM's AMDGPUTargetLowering::LowerUDIVREM */
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static nir_ssa_def *
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emit_udiv(nir_builder *bld, nir_ssa_def *numer, nir_ssa_def *denom, bool modulo)
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{
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nir_ssa_def *rcp = nir_frcp(bld, nir_u2f32(bld, denom));
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rcp = nir_f2u32(bld, nir_fmul_imm(bld, rcp, 4294966784.0));
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nir_ssa_def *neg_rcp_times_denom =
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nir_imul(bld, rcp, nir_ineg(bld, denom));
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rcp = nir_iadd(bld, rcp, nir_umul_high(bld, rcp, neg_rcp_times_denom));
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/* Get initial estimate for quotient/remainder, then refine the estimate
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* in two iterations after */
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nir_ssa_def *quotient = nir_umul_high(bld, numer, rcp);
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nir_ssa_def *num_s_remainder = nir_imul(bld, quotient, denom);
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nir_ssa_def *remainder = nir_isub(bld, numer, num_s_remainder);
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/* First refinement step */
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nir_ssa_def *remainder_ge_den = nir_uge(bld, remainder, denom);
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if (!modulo) {
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quotient = nir_bcsel(bld, remainder_ge_den,
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nir_iadd_imm(bld, quotient, 1), quotient);
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}
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remainder = nir_bcsel(bld, remainder_ge_den,
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nir_isub(bld, remainder, denom), remainder);
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/* Second refinement step */
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remainder_ge_den = nir_uge(bld, remainder, denom);
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if (modulo) {
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return nir_bcsel(bld, remainder_ge_den, nir_isub(bld, remainder, denom),
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remainder);
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} else {
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return nir_bcsel(bld, remainder_ge_den, nir_iadd_imm(bld, quotient, 1),
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quotient);
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}
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}
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/* ported from LLVM's AMDGPUTargetLowering::LowerSDIVREM */
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static nir_ssa_def *
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emit_idiv(nir_builder *bld, nir_ssa_def *numer, nir_ssa_def *denom, nir_op op)
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{
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nir_ssa_def *lh_sign = nir_ilt(bld, numer, nir_imm_int(bld, 0));
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nir_ssa_def *rh_sign = nir_ilt(bld, denom, nir_imm_int(bld, 0));
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lh_sign = nir_bcsel(bld, lh_sign, nir_imm_int(bld, -1), nir_imm_int(bld, 0));
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rh_sign = nir_bcsel(bld, rh_sign, nir_imm_int(bld, -1), nir_imm_int(bld, 0));
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nir_ssa_def *lhs = nir_iadd(bld, numer, lh_sign);
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nir_ssa_def *rhs = nir_iadd(bld, denom, rh_sign);
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lhs = nir_ixor(bld, lhs, lh_sign);
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rhs = nir_ixor(bld, rhs, rh_sign);
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if (op == nir_op_idiv) {
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nir_ssa_def *d_sign = nir_ixor(bld, lh_sign, rh_sign);
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nir_ssa_def *res = emit_udiv(bld, lhs, rhs, false);
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res = nir_ixor(bld, res, d_sign);
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return nir_isub(bld, res, d_sign);
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} else {
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nir_ssa_def *res = emit_udiv(bld, lhs, rhs, true);
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res = nir_ixor(bld, res, lh_sign);
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res = nir_isub(bld, res, lh_sign);
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if (op == nir_op_imod) {
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nir_ssa_def *cond = nir_ieq_imm(bld, res, 0);
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cond = nir_ior(bld, nir_ieq(bld, lh_sign, rh_sign), cond);
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res = nir_bcsel(bld, cond, res, nir_iadd(bld, res, denom));
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}
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return res;
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}
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}
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static nir_ssa_def *
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convert_instr_precise(nir_builder *bld, nir_op op,
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nir_ssa_def *numer, nir_ssa_def *denom)
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{
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if (op == nir_op_udiv || op == nir_op_umod)
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return emit_udiv(bld, numer, denom, op == nir_op_umod);
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else
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return emit_idiv(bld, numer, denom, op);
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}
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static nir_ssa_def *
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convert_instr_small(nir_builder *b, nir_op op,
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nir_ssa_def *numer, nir_ssa_def *denom,
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const nir_lower_idiv_options *options)
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{
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unsigned sz = numer->bit_size;
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nir_alu_type int_type = nir_op_infos[op].output_type | sz;
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nir_alu_type float_type = nir_type_float | (options->allow_fp16 ? sz * 2 : 32);
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nir_ssa_def *p = nir_type_convert(b, numer, int_type, float_type);
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nir_ssa_def *q = nir_type_convert(b, denom, int_type, float_type);
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/* Take 1/q but offset mantissa by 1 to correct for rounding. This is
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* needed for correct results and has been checked exhaustively for
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* all pairs of 16-bit integers */
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nir_ssa_def *rcp = nir_iadd_imm(b, nir_frcp(b, q), 1);
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/* Divide by multiplying by adjusted reciprocal */
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nir_ssa_def *res = nir_fmul(b, p, rcp);
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/* Convert back to integer space with rounding inferred by type */
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res = nir_type_convert(b, res, float_type, int_type);
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/* Get remainder given the quotient */
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if (op == nir_op_umod || op == nir_op_imod || op == nir_op_irem)
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res = nir_isub(b, numer, nir_imul(b, denom, res));
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/* Adjust for sign, see constant folding definition */
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if (op == nir_op_imod) {
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nir_ssa_def *zero = nir_imm_zero(b, 1, sz);
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nir_ssa_def *diff_sign =
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nir_ine(b, nir_ige(b, numer, zero), nir_ige(b, denom, zero));
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nir_ssa_def *adjust = nir_iand(b, diff_sign, nir_ine(b, res, zero));
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res = nir_iadd(b, res, nir_bcsel(b, adjust, denom, zero));
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}
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return res;
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}
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static nir_ssa_def *
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lower_idiv(nir_builder *b, nir_instr *instr, void *_data)
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{
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const nir_lower_idiv_options *options = _data;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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nir_ssa_def *numer = nir_ssa_for_alu_src(b, alu, 0);
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nir_ssa_def *denom = nir_ssa_for_alu_src(b, alu, 1);
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b->exact = true;
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if (numer->bit_size < 32)
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return convert_instr_small(b, alu->op, numer, denom, options);
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else if (options->imprecise_32bit_lowering)
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return convert_instr(b, alu->op, numer, denom);
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else
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return convert_instr_precise(b, alu->op, numer, denom);
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}
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static bool
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inst_is_idiv(const nir_instr *instr, UNUSED const void *_state)
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{
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if (instr->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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if (alu->dest.dest.ssa.bit_size > 32)
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return false;
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switch (alu->op) {
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case nir_op_idiv:
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case nir_op_udiv:
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case nir_op_imod:
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case nir_op_umod:
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case nir_op_irem:
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return true;
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default:
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return false;
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}
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}
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bool
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nir_lower_idiv(nir_shader *shader, const nir_lower_idiv_options *options)
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{
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return nir_shader_lower_instructions(shader,
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inst_is_idiv,
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lower_idiv,
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(void *)options);
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}
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