221 lines
7.3 KiB
C
221 lines
7.3 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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* Copyright © 2019 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jason Ekstrand (jason@jlekstrand.net)
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* Samuel Pitoiset (samuel.pitoiset@gmail.com>
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*/
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#include "nir.h"
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#include "nir_builder.h"
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static nir_ssa_def *
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lower_frexp_sig(nir_builder *b, nir_ssa_def *x)
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{
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nir_ssa_def *abs_x = nir_fabs(b, x);
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nir_ssa_def *zero = nir_imm_floatN_t(b, 0, x->bit_size);
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nir_ssa_def *sign_mantissa_mask, *exponent_value;
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switch (x->bit_size) {
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case 16:
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/* Half-precision floating-point values are stored as
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* 1 sign bit;
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* 5 exponent bits;
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* 10 mantissa bits.
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*
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* An exponent shift of 10 will shift the mantissa out, leaving only the
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* exponent and sign bit (which itself may be zero, if the absolute value
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* was taken before the bitcast and shift).
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*/
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sign_mantissa_mask = nir_imm_intN_t(b, 0x83ffu, 16);
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/* Exponent of floating-point values in the range [0.5, 1.0). */
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exponent_value = nir_imm_intN_t(b, 0x3800u, 16);
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break;
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case 32:
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/* Single-precision floating-point values are stored as
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* 1 sign bit;
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* 8 exponent bits;
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* 23 mantissa bits.
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*
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* An exponent shift of 23 will shift the mantissa out, leaving only the
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* exponent and sign bit (which itself may be zero, if the absolute value
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* was taken before the bitcast and shift.
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*/
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sign_mantissa_mask = nir_imm_int(b, 0x807fffffu);
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/* Exponent of floating-point values in the range [0.5, 1.0). */
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exponent_value = nir_imm_int(b, 0x3f000000u);
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break;
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case 64:
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/* Double-precision floating-point values are stored as
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* 1 sign bit;
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* 11 exponent bits;
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* 52 mantissa bits.
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*
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* An exponent shift of 20 will shift the remaining mantissa bits out,
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* leaving only the exponent and sign bit (which itself may be zero, if
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* the absolute value was taken before the bitcast and shift.
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*/
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sign_mantissa_mask = nir_imm_int(b, 0x800fffffu);
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/* Exponent of floating-point values in the range [0.5, 1.0). */
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exponent_value = nir_imm_int(b, 0x3fe00000u);
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break;
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default:
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unreachable("Invalid bitsize");
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}
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if (x->bit_size == 64) {
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/* We only need to deal with the exponent so first we extract the upper
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* 32 bits using nir_unpack_64_2x32_split_y.
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*/
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nir_ssa_def *upper_x = nir_unpack_64_2x32_split_y(b, x);
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/* If x is ±0, ±Inf, or NaN, return x unmodified. */
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nir_ssa_def *new_upper =
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nir_bcsel(b,
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nir_iand(b,
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nir_flt(b, zero, abs_x),
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nir_fisfinite(b, x)),
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nir_ior(b,
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nir_iand(b, upper_x, sign_mantissa_mask),
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exponent_value),
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upper_x);
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nir_ssa_def *lower_x = nir_unpack_64_2x32_split_x(b, x);
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return nir_pack_64_2x32_split(b, lower_x, new_upper);
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} else {
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/* If x is ±0, ±Inf, or NaN, return x unmodified. */
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return nir_bcsel(b,
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nir_iand(b,
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nir_flt(b, zero, abs_x),
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nir_fisfinite(b, x)),
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nir_ior(b,
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nir_iand(b, x, sign_mantissa_mask),
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exponent_value),
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x);
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}
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}
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static nir_ssa_def *
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lower_frexp_exp(nir_builder *b, nir_ssa_def *x)
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{
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nir_ssa_def *abs_x = nir_fabs(b, x);
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nir_ssa_def *zero = nir_imm_floatN_t(b, 0, x->bit_size);
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nir_ssa_def *is_not_zero = nir_fneu(b, abs_x, zero);
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nir_ssa_def *exponent;
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switch (x->bit_size) {
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case 16: {
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nir_ssa_def *exponent_shift = nir_imm_int(b, 10);
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nir_ssa_def *exponent_bias = nir_imm_intN_t(b, -14, 16);
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/* Significand return must be of the same type as the input, but the
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* exponent must be a 32-bit integer.
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*/
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exponent = nir_i2i32(b, nir_iadd(b, nir_ushr(b, abs_x, exponent_shift),
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nir_bcsel(b, is_not_zero, exponent_bias, zero)));
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break;
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}
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case 32: {
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nir_ssa_def *exponent_shift = nir_imm_int(b, 23);
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nir_ssa_def *exponent_bias = nir_imm_int(b, -126);
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exponent = nir_iadd(b, nir_ushr(b, abs_x, exponent_shift),
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nir_bcsel(b, is_not_zero, exponent_bias, zero));
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break;
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}
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case 64: {
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nir_ssa_def *exponent_shift = nir_imm_int(b, 20);
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nir_ssa_def *exponent_bias = nir_imm_int(b, -1022);
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nir_ssa_def *zero32 = nir_imm_int(b, 0);
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nir_ssa_def *abs_upper_x = nir_unpack_64_2x32_split_y(b, abs_x);
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exponent = nir_iadd(b, nir_ushr(b, abs_upper_x, exponent_shift),
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nir_bcsel(b, is_not_zero, exponent_bias, zero32));
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break;
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}
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default:
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unreachable("Invalid bitsize");
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}
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return exponent;
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}
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static bool
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lower_frexp_impl(nir_function_impl *impl)
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{
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bool progress = false;
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nir_builder b;
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nir_builder_init(&b, impl);
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_alu)
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continue;
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nir_alu_instr *alu_instr = nir_instr_as_alu(instr);
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nir_ssa_def *lower;
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b.cursor = nir_before_instr(instr);
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switch (alu_instr->op) {
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case nir_op_frexp_sig:
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lower = lower_frexp_sig(&b, nir_ssa_for_alu_src(&b, alu_instr, 0));
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break;
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case nir_op_frexp_exp:
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lower = lower_frexp_exp(&b, nir_ssa_for_alu_src(&b, alu_instr, 0));
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break;
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default:
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continue;
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}
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nir_ssa_def_rewrite_uses(&alu_instr->dest.dest.ssa,
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lower);
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nir_instr_remove(instr);
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progress = true;
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}
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}
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if (progress) {
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nir_metadata_preserve(impl, nir_metadata_block_index |
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nir_metadata_dominance);
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}
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return progress;
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}
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bool
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nir_lower_frexp(nir_shader *shader)
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{
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bool progress = false;
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nir_foreach_function(function, shader) {
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if (function->impl)
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progress |= lower_frexp_impl(function->impl);
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}
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return progress;
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}
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