1137 lines
38 KiB
C
1137 lines
38 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jason Ekstrand (jason@jlekstrand.net)
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*
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*/
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#include "nir.h"
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#include "nir_builder.h"
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#include "nir_vla.h"
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/*
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* This file implements an out-of-SSA pass as described in "Revisiting
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* Out-of-SSA Translation for Correctness, Code Quality, and Efficiency" by
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* Boissinot et al.
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*/
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struct from_ssa_state {
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nir_builder builder;
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void *dead_ctx;
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struct exec_list dead_instrs;
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bool phi_webs_only;
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struct hash_table *merge_node_table;
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nir_instr *instr;
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bool progress;
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};
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/* Returns if def @a comes after def @b.
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*
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* The core observation that makes the Boissinot algorithm efficient
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* is that, given two properly sorted sets, we can check for
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* interference in these sets via a linear walk. This is accomplished
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* by doing single combined walk over union of the two sets in DFS
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* order. It doesn't matter what DFS we do so long as we're
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* consistent. Fortunately, the dominance algorithm we ran prior to
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* this pass did such a walk and recorded the pre- and post-indices in
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* the blocks.
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*
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* We treat SSA undefs as always coming before other instruction types.
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*/
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static bool
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def_after(nir_ssa_def *a, nir_ssa_def *b)
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{
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if (a->parent_instr->type == nir_instr_type_ssa_undef)
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return false;
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if (b->parent_instr->type == nir_instr_type_ssa_undef)
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return true;
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/* If they're in the same block, we can rely on whichever instruction
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* comes first in the block.
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*/
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if (a->parent_instr->block == b->parent_instr->block)
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return a->parent_instr->index > b->parent_instr->index;
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/* Otherwise, if blocks are distinct, we sort them in DFS pre-order */
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return a->parent_instr->block->dom_pre_index >
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b->parent_instr->block->dom_pre_index;
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}
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/* Returns true if a dominates b */
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static bool
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ssa_def_dominates(nir_ssa_def *a, nir_ssa_def *b)
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{
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if (a->parent_instr->type == nir_instr_type_ssa_undef) {
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/* SSA undefs always dominate */
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return true;
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} if (def_after(a, b)) {
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return false;
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} else if (a->parent_instr->block == b->parent_instr->block) {
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return def_after(b, a);
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} else {
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return nir_block_dominates(a->parent_instr->block,
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b->parent_instr->block);
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}
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}
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/* The following data structure, which I have named merge_set is a way of
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* representing a set registers of non-interfering registers. This is
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* based on the concept of a "dominance forest" presented in "Fast Copy
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* Coalescing and Live-Range Identification" by Budimlic et al. but the
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* implementation concept is taken from "Revisiting Out-of-SSA Translation
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* for Correctness, Code Quality, and Efficiency" by Boissinot et al.
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*
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* Each SSA definition is associated with a merge_node and the association
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* is represented by a combination of a hash table and the "def" parameter
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* in the merge_node structure. The merge_set stores a linked list of
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* merge_nodes, ordered by a pre-order DFS walk of the dominance tree. (Since
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* the liveness analysis pass indexes the SSA values in dominance order for
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* us, this is an easy thing to keep up.) It is assumed that no pair of the
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* nodes in a given set interfere. Merging two sets or checking for
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* interference can be done in a single linear-time merge-sort walk of the
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* two lists of nodes.
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*/
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struct merge_set;
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typedef struct {
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struct exec_node node;
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struct merge_set *set;
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nir_ssa_def *def;
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} merge_node;
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typedef struct merge_set {
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struct exec_list nodes;
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unsigned size;
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bool divergent;
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nir_register *reg;
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} merge_set;
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#if 0
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static void
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merge_set_dump(merge_set *set, FILE *fp)
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{
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nir_ssa_def *dom[set->size];
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int dom_idx = -1;
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foreach_list_typed(merge_node, node, node, &set->nodes) {
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while (dom_idx >= 0 && !ssa_def_dominates(dom[dom_idx], node->def))
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dom_idx--;
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for (int i = 0; i <= dom_idx; i++)
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fprintf(fp, " ");
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fprintf(fp, "ssa_%d\n", node->def->index);
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dom[++dom_idx] = node->def;
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}
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}
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#endif
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static merge_node *
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get_merge_node(nir_ssa_def *def, struct from_ssa_state *state)
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{
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struct hash_entry *entry =
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_mesa_hash_table_search(state->merge_node_table, def);
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if (entry)
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return entry->data;
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merge_set *set = ralloc(state->dead_ctx, merge_set);
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exec_list_make_empty(&set->nodes);
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set->size = 1;
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set->divergent = def->divergent;
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set->reg = NULL;
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merge_node *node = ralloc(state->dead_ctx, merge_node);
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node->set = set;
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node->def = def;
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exec_list_push_head(&set->nodes, &node->node);
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_mesa_hash_table_insert(state->merge_node_table, def, node);
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return node;
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}
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static bool
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merge_nodes_interfere(merge_node *a, merge_node *b)
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{
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/* There's no need to check for interference within the same set,
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* because we assume, that sets themselves are already
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* interference-free.
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*/
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if (a->set == b->set)
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return false;
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return nir_ssa_defs_interfere(a->def, b->def);
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}
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/* Merges b into a
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*
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* This algorithm uses def_after to ensure that the sets always stay in the
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* same order as the pre-order DFS done by the liveness algorithm.
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*/
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static merge_set *
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merge_merge_sets(merge_set *a, merge_set *b)
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{
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struct exec_node *an = exec_list_get_head(&a->nodes);
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struct exec_node *bn = exec_list_get_head(&b->nodes);
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while (!exec_node_is_tail_sentinel(bn)) {
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merge_node *a_node = exec_node_data(merge_node, an, node);
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merge_node *b_node = exec_node_data(merge_node, bn, node);
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if (exec_node_is_tail_sentinel(an) ||
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def_after(a_node->def, b_node->def)) {
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struct exec_node *next = bn->next;
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exec_node_remove(bn);
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exec_node_insert_node_before(an, bn);
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exec_node_data(merge_node, bn, node)->set = a;
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bn = next;
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} else {
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an = an->next;
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}
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}
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a->size += b->size;
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b->size = 0;
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a->divergent |= b->divergent;
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return a;
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}
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/* Checks for any interference between two merge sets
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*
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* This is an implementation of Algorithm 2 in "Revisiting Out-of-SSA
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* Translation for Correctness, Code Quality, and Efficiency" by
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* Boissinot et al.
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*/
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static bool
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merge_sets_interfere(merge_set *a, merge_set *b)
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{
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/* List of all the nodes which dominate the current node, in dominance
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* order.
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*/
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NIR_VLA(merge_node *, dom, a->size + b->size);
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int dom_idx = -1;
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struct exec_node *an = exec_list_get_head(&a->nodes);
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struct exec_node *bn = exec_list_get_head(&b->nodes);
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while (!exec_node_is_tail_sentinel(an) ||
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!exec_node_is_tail_sentinel(bn)) {
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/* We walk the union of the two sets in the same order as the pre-order
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* DFS done by liveness analysis.
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*/
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merge_node *current;
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if (exec_node_is_tail_sentinel(an)) {
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current = exec_node_data(merge_node, bn, node);
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bn = bn->next;
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} else if (exec_node_is_tail_sentinel(bn)) {
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current = exec_node_data(merge_node, an, node);
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an = an->next;
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} else {
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merge_node *a_node = exec_node_data(merge_node, an, node);
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merge_node *b_node = exec_node_data(merge_node, bn, node);
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if (def_after(b_node->def, a_node->def)) {
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current = a_node;
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an = an->next;
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} else {
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current = b_node;
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bn = bn->next;
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}
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}
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/* Because our walk is a pre-order DFS, we can maintain the list of
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* dominating nodes as a simple stack, pushing every node onto the list
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* after we visit it and popping any non-dominating nodes off before we
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* visit the current node.
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*/
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while (dom_idx >= 0 &&
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!ssa_def_dominates(dom[dom_idx]->def, current->def))
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dom_idx--;
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/* There are three invariants of this algorithm that are important here:
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*
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* 1. There is no interference within either set a or set b.
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* 2. None of the nodes processed up until this point interfere.
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* 3. All the dominators of `current` have been processed
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*
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* Because of these invariants, we only need to check the current node
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* against its minimal dominator. If any other node N in the union
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* interferes with current, then N must dominate current because we are
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* in SSA form. If N dominates current then it must also dominate our
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* minimal dominator dom[dom_idx]. Since N is live at current it must
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* also be live at the minimal dominator which means N interferes with
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* the minimal dominator dom[dom_idx] and, by invariants 2 and 3 above,
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* the algorithm would have already terminated. Therefore, if we got
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* here, the only node that can possibly interfere with current is the
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* minimal dominator dom[dom_idx].
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*
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* This is what allows us to do a interference check of the union of the
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* two sets with a single linear-time walk.
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*/
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if (dom_idx >= 0 && merge_nodes_interfere(current, dom[dom_idx]))
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return true;
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dom[++dom_idx] = current;
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}
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return false;
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}
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static bool
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add_parallel_copy_to_end_of_block(nir_shader *shader, nir_block *block, void *dead_ctx)
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{
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bool need_end_copy = false;
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if (block->successors[0]) {
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nir_instr *instr = nir_block_first_instr(block->successors[0]);
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if (instr && instr->type == nir_instr_type_phi)
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need_end_copy = true;
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}
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if (block->successors[1]) {
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nir_instr *instr = nir_block_first_instr(block->successors[1]);
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if (instr && instr->type == nir_instr_type_phi)
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need_end_copy = true;
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}
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if (need_end_copy) {
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/* If one of our successors has at least one phi node, we need to
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* create a parallel copy at the end of the block but before the jump
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* (if there is one).
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*/
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nir_parallel_copy_instr *pcopy =
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nir_parallel_copy_instr_create(shader);
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nir_instr_insert(nir_after_block_before_jump(block), &pcopy->instr);
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}
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return true;
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}
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static nir_parallel_copy_instr *
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get_parallel_copy_at_end_of_block(nir_block *block)
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{
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nir_instr *last_instr = nir_block_last_instr(block);
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if (last_instr == NULL)
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return NULL;
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/* The last instruction may be a jump in which case the parallel copy is
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* right before it.
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*/
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if (last_instr->type == nir_instr_type_jump)
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last_instr = nir_instr_prev(last_instr);
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if (last_instr && last_instr->type == nir_instr_type_parallel_copy)
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return nir_instr_as_parallel_copy(last_instr);
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else
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return NULL;
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}
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/** Isolate phi nodes with parallel copies
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*
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* In order to solve the dependency problems with the sources and
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* destinations of phi nodes, we first isolate them by adding parallel
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* copies to the beginnings and ends of basic blocks. For every block with
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* phi nodes, we add a parallel copy immediately following the last phi
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* node that copies the destinations of all of the phi nodes to new SSA
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* values. We also add a parallel copy to the end of every block that has
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* a successor with phi nodes that, for each phi node in each successor,
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* copies the corresponding sorce of the phi node and adjust the phi to
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* used the destination of the parallel copy.
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*
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* In SSA form, each value has exactly one definition. What this does is
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* ensure that each value used in a phi also has exactly one use. The
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* destinations of phis are only used by the parallel copy immediately
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* following the phi nodes and. Thanks to the parallel copy at the end of
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* the predecessor block, the sources of phi nodes are are the only use of
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* that value. This allows us to immediately assign all the sources and
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* destinations of any given phi node to the same register without worrying
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* about interference at all. We do coalescing to get rid of the parallel
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* copies where possible.
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*
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* Before this pass can be run, we have to iterate over the blocks with
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* add_parallel_copy_to_end_of_block to ensure that the parallel copies at
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* the ends of blocks exist. We can create the ones at the beginnings as
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* we go, but the ones at the ends of blocks need to be created ahead of
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* time because of potential back-edges in the CFG.
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*/
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static bool
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isolate_phi_nodes_block(nir_shader *shader, nir_block *block, void *dead_ctx)
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{
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nir_instr *last_phi_instr = NULL;
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nir_foreach_instr(instr, block) {
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/* Phi nodes only ever come at the start of a block */
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if (instr->type != nir_instr_type_phi)
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break;
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last_phi_instr = instr;
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}
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/* If we don't have any phis, then there's nothing for us to do. */
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if (last_phi_instr == NULL)
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return true;
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/* If we have phi nodes, we need to create a parallel copy at the
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* start of this block but after the phi nodes.
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*/
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nir_parallel_copy_instr *block_pcopy =
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nir_parallel_copy_instr_create(shader);
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nir_instr_insert_after(last_phi_instr, &block_pcopy->instr);
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nir_foreach_instr(instr, block) {
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/* Phi nodes only ever come at the start of a block */
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if (instr->type != nir_instr_type_phi)
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break;
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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assert(phi->dest.is_ssa);
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nir_foreach_phi_src(src, phi) {
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nir_parallel_copy_instr *pcopy =
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get_parallel_copy_at_end_of_block(src->pred);
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assert(pcopy);
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nir_parallel_copy_entry *entry = rzalloc(dead_ctx,
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nir_parallel_copy_entry);
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nir_ssa_dest_init(&pcopy->instr, &entry->dest,
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phi->dest.ssa.num_components,
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phi->dest.ssa.bit_size, NULL);
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entry->dest.ssa.divergent = nir_src_is_divergent(src->src);
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exec_list_push_tail(&pcopy->entries, &entry->node);
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assert(src->src.is_ssa);
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nir_instr_rewrite_src(&pcopy->instr, &entry->src, src->src);
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nir_instr_rewrite_src(&phi->instr, &src->src,
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nir_src_for_ssa(&entry->dest.ssa));
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}
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nir_parallel_copy_entry *entry = rzalloc(dead_ctx,
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nir_parallel_copy_entry);
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nir_ssa_dest_init(&block_pcopy->instr, &entry->dest,
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phi->dest.ssa.num_components, phi->dest.ssa.bit_size,
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NULL);
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entry->dest.ssa.divergent = phi->dest.ssa.divergent;
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exec_list_push_tail(&block_pcopy->entries, &entry->node);
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nir_ssa_def_rewrite_uses(&phi->dest.ssa,
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&entry->dest.ssa);
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nir_instr_rewrite_src(&block_pcopy->instr, &entry->src,
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nir_src_for_ssa(&phi->dest.ssa));
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}
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return true;
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}
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static bool
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coalesce_phi_nodes_block(nir_block *block, struct from_ssa_state *state)
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{
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nir_foreach_instr(instr, block) {
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/* Phi nodes only ever come at the start of a block */
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if (instr->type != nir_instr_type_phi)
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break;
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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assert(phi->dest.is_ssa);
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merge_node *dest_node = get_merge_node(&phi->dest.ssa, state);
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nir_foreach_phi_src(src, phi) {
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assert(src->src.is_ssa);
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merge_node *src_node = get_merge_node(src->src.ssa, state);
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if (src_node->set != dest_node->set)
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merge_merge_sets(dest_node->set, src_node->set);
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}
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}
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return true;
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}
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|
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static void
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aggressive_coalesce_parallel_copy(nir_parallel_copy_instr *pcopy,
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struct from_ssa_state *state)
|
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{
|
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nir_foreach_parallel_copy_entry(entry, pcopy) {
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if (!entry->src.is_ssa)
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continue;
|
|
|
|
/* Since load_const instructions are SSA only, we can't replace their
|
|
* destinations with registers and, therefore, can't coalesce them.
|
|
*/
|
|
if (entry->src.ssa->parent_instr->type == nir_instr_type_load_const)
|
|
continue;
|
|
|
|
/* Don't try and coalesce these */
|
|
if (entry->dest.ssa.num_components != entry->src.ssa->num_components)
|
|
continue;
|
|
|
|
merge_node *src_node = get_merge_node(entry->src.ssa, state);
|
|
merge_node *dest_node = get_merge_node(&entry->dest.ssa, state);
|
|
|
|
if (src_node->set == dest_node->set)
|
|
continue;
|
|
|
|
/* TODO: We can probably do better here but for now we should be safe if
|
|
* we just don't coalesce things with different divergence.
|
|
*/
|
|
if (dest_node->set->divergent != src_node->set->divergent)
|
|
continue;
|
|
|
|
if (!merge_sets_interfere(src_node->set, dest_node->set))
|
|
merge_merge_sets(src_node->set, dest_node->set);
|
|
}
|
|
}
|
|
|
|
static bool
|
|
aggressive_coalesce_block(nir_block *block, struct from_ssa_state *state)
|
|
{
|
|
nir_parallel_copy_instr *start_pcopy = NULL;
|
|
nir_foreach_instr(instr, block) {
|
|
/* Phi nodes only ever come at the start of a block */
|
|
if (instr->type != nir_instr_type_phi) {
|
|
if (instr->type != nir_instr_type_parallel_copy)
|
|
break; /* The parallel copy must be right after the phis */
|
|
|
|
start_pcopy = nir_instr_as_parallel_copy(instr);
|
|
|
|
aggressive_coalesce_parallel_copy(start_pcopy, state);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
nir_parallel_copy_instr *end_pcopy =
|
|
get_parallel_copy_at_end_of_block(block);
|
|
|
|
if (end_pcopy && end_pcopy != start_pcopy)
|
|
aggressive_coalesce_parallel_copy(end_pcopy, state);
|
|
|
|
return true;
|
|
}
|
|
|
|
static nir_register *
|
|
create_reg_for_ssa_def(nir_ssa_def *def, nir_function_impl *impl)
|
|
{
|
|
nir_register *reg = nir_local_reg_create(impl);
|
|
|
|
reg->num_components = def->num_components;
|
|
reg->bit_size = def->bit_size;
|
|
reg->num_array_elems = 0;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static bool
|
|
rewrite_ssa_def(nir_ssa_def *def, void *void_state)
|
|
{
|
|
struct from_ssa_state *state = void_state;
|
|
nir_register *reg;
|
|
|
|
struct hash_entry *entry =
|
|
_mesa_hash_table_search(state->merge_node_table, def);
|
|
if (entry) {
|
|
/* In this case, we're part of a phi web. Use the web's register. */
|
|
merge_node *node = (merge_node *)entry->data;
|
|
|
|
/* If it doesn't have a register yet, create one. Note that all of
|
|
* the things in the merge set should be the same so it doesn't
|
|
* matter which node's definition we use.
|
|
*/
|
|
if (node->set->reg == NULL) {
|
|
node->set->reg = create_reg_for_ssa_def(def, state->builder.impl);
|
|
node->set->reg->divergent = node->set->divergent;
|
|
}
|
|
|
|
reg = node->set->reg;
|
|
} else {
|
|
if (state->phi_webs_only)
|
|
return true;
|
|
|
|
/* We leave load_const SSA values alone. They act as immediates to
|
|
* the backend. If it got coalesced into a phi, that's ok.
|
|
*/
|
|
if (def->parent_instr->type == nir_instr_type_load_const)
|
|
return true;
|
|
|
|
reg = create_reg_for_ssa_def(def, state->builder.impl);
|
|
}
|
|
|
|
nir_ssa_def_rewrite_uses_src(def, nir_src_for_reg(reg));
|
|
assert(nir_ssa_def_is_unused(def));
|
|
|
|
if (def->parent_instr->type == nir_instr_type_ssa_undef) {
|
|
/* If it's an ssa_undef instruction, remove it since we know we just got
|
|
* rid of all its uses.
|
|
*/
|
|
nir_instr *parent_instr = def->parent_instr;
|
|
nir_instr_remove(parent_instr);
|
|
exec_list_push_tail(&state->dead_instrs, &parent_instr->node);
|
|
state->progress = true;
|
|
return true;
|
|
}
|
|
|
|
assert(def->parent_instr->type != nir_instr_type_load_const);
|
|
|
|
/* At this point we know a priori that this SSA def is part of a
|
|
* nir_dest. We can use exec_node_data to get the dest pointer.
|
|
*/
|
|
nir_dest *dest = exec_node_data(nir_dest, def, ssa);
|
|
|
|
nir_instr_rewrite_dest(state->instr, dest, nir_dest_for_reg(reg));
|
|
state->progress = true;
|
|
return true;
|
|
}
|
|
|
|
/* Resolves ssa definitions to registers. While we're at it, we also
|
|
* remove phi nodes.
|
|
*/
|
|
static void
|
|
resolve_registers_block(nir_block *block, struct from_ssa_state *state)
|
|
{
|
|
nir_foreach_instr_safe(instr, block) {
|
|
state->instr = instr;
|
|
nir_foreach_ssa_def(instr, rewrite_ssa_def, state);
|
|
|
|
if (instr->type == nir_instr_type_phi) {
|
|
nir_instr_remove(instr);
|
|
exec_list_push_tail(&state->dead_instrs, &instr->node);
|
|
state->progress = true;
|
|
}
|
|
}
|
|
state->instr = NULL;
|
|
}
|
|
|
|
static void
|
|
emit_copy(nir_builder *b, nir_src src, nir_src dest_src)
|
|
{
|
|
assert(!dest_src.is_ssa &&
|
|
dest_src.reg.indirect == NULL &&
|
|
dest_src.reg.base_offset == 0);
|
|
|
|
assert(!nir_src_is_divergent(src) || nir_src_is_divergent(dest_src));
|
|
|
|
if (src.is_ssa)
|
|
assert(src.ssa->num_components >= dest_src.reg.reg->num_components);
|
|
else
|
|
assert(src.reg.reg->num_components >= dest_src.reg.reg->num_components);
|
|
|
|
nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
|
|
nir_src_copy(&mov->src[0].src, &src);
|
|
mov->dest.dest = nir_dest_for_reg(dest_src.reg.reg);
|
|
mov->dest.write_mask = (1 << dest_src.reg.reg->num_components) - 1;
|
|
|
|
nir_builder_instr_insert(b, &mov->instr);
|
|
}
|
|
|
|
/* Resolves a single parallel copy operation into a sequence of movs
|
|
*
|
|
* This is based on Algorithm 1 from "Revisiting Out-of-SSA Translation for
|
|
* Correctness, Code Quality, and Efficiency" by Boissinot et al.
|
|
* However, I never got the algorithm to work as written, so this version
|
|
* is slightly modified.
|
|
*
|
|
* The algorithm works by playing this little shell game with the values.
|
|
* We start by recording where every source value is and which source value
|
|
* each destination value should receive. We then grab any copy whose
|
|
* destination is "empty", i.e. not used as a source, and do the following:
|
|
* - Find where its source value currently lives
|
|
* - Emit the move instruction
|
|
* - Set the location of the source value to the destination
|
|
* - Mark the location containing the source value
|
|
* - Mark the destination as no longer needing to be copied
|
|
*
|
|
* When we run out of "empty" destinations, we have a cycle and so we
|
|
* create a temporary register, copy to that register, and mark the value
|
|
* we copied as living in that temporary. Now, the cycle is broken, so we
|
|
* can continue with the above steps.
|
|
*/
|
|
static void
|
|
resolve_parallel_copy(nir_parallel_copy_instr *pcopy,
|
|
struct from_ssa_state *state)
|
|
{
|
|
unsigned num_copies = 0;
|
|
nir_foreach_parallel_copy_entry(entry, pcopy) {
|
|
/* Sources may be SSA */
|
|
if (!entry->src.is_ssa && entry->src.reg.reg == entry->dest.reg.reg)
|
|
continue;
|
|
|
|
num_copies++;
|
|
}
|
|
|
|
if (num_copies == 0) {
|
|
/* Hooray, we don't need any copies! */
|
|
nir_instr_remove(&pcopy->instr);
|
|
exec_list_push_tail(&state->dead_instrs, &pcopy->instr.node);
|
|
return;
|
|
}
|
|
|
|
/* The register/source corresponding to the given index */
|
|
NIR_VLA_ZERO(nir_src, values, num_copies * 2);
|
|
|
|
/* The current location of a given piece of data. We will use -1 for "null" */
|
|
NIR_VLA_FILL(int, loc, num_copies * 2, -1);
|
|
|
|
/* The piece of data that the given piece of data is to be copied from. We will use -1 for "null" */
|
|
NIR_VLA_FILL(int, pred, num_copies * 2, -1);
|
|
|
|
/* The destinations we have yet to properly fill */
|
|
NIR_VLA(int, to_do, num_copies * 2);
|
|
int to_do_idx = -1;
|
|
|
|
state->builder.cursor = nir_before_instr(&pcopy->instr);
|
|
|
|
/* Now we set everything up:
|
|
* - All values get assigned a temporary index
|
|
* - Current locations are set from sources
|
|
* - Predicessors are recorded from sources and destinations
|
|
*/
|
|
int num_vals = 0;
|
|
nir_foreach_parallel_copy_entry(entry, pcopy) {
|
|
/* Sources may be SSA */
|
|
if (!entry->src.is_ssa && entry->src.reg.reg == entry->dest.reg.reg)
|
|
continue;
|
|
|
|
int src_idx = -1;
|
|
for (int i = 0; i < num_vals; ++i) {
|
|
if (nir_srcs_equal(values[i], entry->src))
|
|
src_idx = i;
|
|
}
|
|
if (src_idx < 0) {
|
|
src_idx = num_vals++;
|
|
values[src_idx] = entry->src;
|
|
}
|
|
|
|
nir_src dest_src = nir_src_for_reg(entry->dest.reg.reg);
|
|
|
|
int dest_idx = -1;
|
|
for (int i = 0; i < num_vals; ++i) {
|
|
if (nir_srcs_equal(values[i], dest_src)) {
|
|
/* Each destination of a parallel copy instruction should be
|
|
* unique. A destination may get used as a source, so we still
|
|
* have to walk the list. However, the predecessor should not,
|
|
* at this point, be set yet, so we should have -1 here.
|
|
*/
|
|
assert(pred[i] == -1);
|
|
dest_idx = i;
|
|
}
|
|
}
|
|
if (dest_idx < 0) {
|
|
dest_idx = num_vals++;
|
|
values[dest_idx] = dest_src;
|
|
}
|
|
|
|
loc[src_idx] = src_idx;
|
|
pred[dest_idx] = src_idx;
|
|
|
|
to_do[++to_do_idx] = dest_idx;
|
|
}
|
|
|
|
/* Currently empty destinations we can go ahead and fill */
|
|
NIR_VLA(int, ready, num_copies * 2);
|
|
int ready_idx = -1;
|
|
|
|
/* Mark the ones that are ready for copying. We know an index is a
|
|
* destination if it has a predecessor and it's ready for copying if
|
|
* it's not marked as containing data.
|
|
*/
|
|
for (int i = 0; i < num_vals; i++) {
|
|
if (pred[i] != -1 && loc[i] == -1)
|
|
ready[++ready_idx] = i;
|
|
}
|
|
|
|
while (to_do_idx >= 0) {
|
|
while (ready_idx >= 0) {
|
|
int b = ready[ready_idx--];
|
|
int a = pred[b];
|
|
emit_copy(&state->builder, values[loc[a]], values[b]);
|
|
|
|
/* b has been filled, mark it as not needing to be copied */
|
|
pred[b] = -1;
|
|
|
|
/* The next bit only applies if the source and destination have the
|
|
* same divergence. If they differ (it must be convergent ->
|
|
* divergent), then we can't guarantee we won't need the convergent
|
|
* version of again.
|
|
*/
|
|
if (nir_src_is_divergent(values[a]) ==
|
|
nir_src_is_divergent(values[b])) {
|
|
/* If any other copies want a they can find it at b but only if the
|
|
* two have the same divergence.
|
|
*/
|
|
loc[a] = b;
|
|
|
|
/* If a needs to be filled... */
|
|
if (pred[a] != -1) {
|
|
/* If any other copies want a they can find it at b */
|
|
loc[a] = b;
|
|
|
|
/* It's ready for copying now */
|
|
ready[++ready_idx] = a;
|
|
}
|
|
}
|
|
}
|
|
int b = to_do[to_do_idx--];
|
|
if (pred[b] == -1)
|
|
continue;
|
|
|
|
/* If we got here, then we don't have any more trivial copies that we
|
|
* can do. We have to break a cycle, so we create a new temporary
|
|
* register for that purpose. Normally, if going out of SSA after
|
|
* register allocation, you would want to avoid creating temporary
|
|
* registers. However, we are going out of SSA before register
|
|
* allocation, so we would rather not create extra register
|
|
* dependencies for the backend to deal with. If it wants, the
|
|
* backend can coalesce the (possibly multiple) temporaries.
|
|
*/
|
|
assert(num_vals < num_copies * 2);
|
|
nir_register *reg = nir_local_reg_create(state->builder.impl);
|
|
reg->num_array_elems = 0;
|
|
if (values[b].is_ssa) {
|
|
reg->num_components = values[b].ssa->num_components;
|
|
reg->bit_size = values[b].ssa->bit_size;
|
|
} else {
|
|
reg->num_components = values[b].reg.reg->num_components;
|
|
reg->bit_size = values[b].reg.reg->bit_size;
|
|
}
|
|
reg->divergent = nir_src_is_divergent(values[b]);
|
|
values[num_vals].is_ssa = false;
|
|
values[num_vals].reg.reg = reg;
|
|
|
|
emit_copy(&state->builder, values[b], values[num_vals]);
|
|
loc[b] = num_vals;
|
|
ready[++ready_idx] = b;
|
|
num_vals++;
|
|
}
|
|
|
|
nir_instr_remove(&pcopy->instr);
|
|
exec_list_push_tail(&state->dead_instrs, &pcopy->instr.node);
|
|
}
|
|
|
|
/* Resolves the parallel copies in a block. Each block can have at most
|
|
* two: One at the beginning, right after all the phi noces, and one at
|
|
* the end (or right before the final jump if it exists).
|
|
*/
|
|
static bool
|
|
resolve_parallel_copies_block(nir_block *block, struct from_ssa_state *state)
|
|
{
|
|
/* At this point, we have removed all of the phi nodes. If a parallel
|
|
* copy existed right after the phi nodes in this block, it is now the
|
|
* first instruction.
|
|
*/
|
|
nir_instr *first_instr = nir_block_first_instr(block);
|
|
if (first_instr == NULL)
|
|
return true; /* Empty, nothing to do. */
|
|
|
|
if (first_instr->type == nir_instr_type_parallel_copy) {
|
|
nir_parallel_copy_instr *pcopy = nir_instr_as_parallel_copy(first_instr);
|
|
|
|
resolve_parallel_copy(pcopy, state);
|
|
}
|
|
|
|
/* It's possible that the above code already cleaned up the end parallel
|
|
* copy. However, doing so removed it form the instructions list so we
|
|
* won't find it here. Therefore, it's safe to go ahead and just look
|
|
* for one and clean it up if it exists.
|
|
*/
|
|
nir_parallel_copy_instr *end_pcopy =
|
|
get_parallel_copy_at_end_of_block(block);
|
|
if (end_pcopy)
|
|
resolve_parallel_copy(end_pcopy, state);
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
nir_convert_from_ssa_impl(nir_function_impl *impl, bool phi_webs_only)
|
|
{
|
|
nir_shader *shader = impl->function->shader;
|
|
|
|
struct from_ssa_state state;
|
|
|
|
nir_builder_init(&state.builder, impl);
|
|
state.dead_ctx = ralloc_context(NULL);
|
|
state.phi_webs_only = phi_webs_only;
|
|
state.merge_node_table = _mesa_pointer_hash_table_create(NULL);
|
|
state.progress = false;
|
|
exec_list_make_empty(&state.dead_instrs);
|
|
|
|
nir_foreach_block(block, impl) {
|
|
add_parallel_copy_to_end_of_block(shader, block, state.dead_ctx);
|
|
}
|
|
|
|
nir_foreach_block(block, impl) {
|
|
isolate_phi_nodes_block(shader, block, state.dead_ctx);
|
|
}
|
|
|
|
/* Mark metadata as dirty before we ask for liveness analysis */
|
|
nir_metadata_preserve(impl, nir_metadata_block_index |
|
|
nir_metadata_dominance);
|
|
|
|
nir_metadata_require(impl, nir_metadata_instr_index |
|
|
nir_metadata_live_ssa_defs |
|
|
nir_metadata_dominance);
|
|
|
|
nir_foreach_block(block, impl) {
|
|
coalesce_phi_nodes_block(block, &state);
|
|
}
|
|
|
|
nir_foreach_block(block, impl) {
|
|
aggressive_coalesce_block(block, &state);
|
|
}
|
|
|
|
nir_foreach_block(block, impl) {
|
|
resolve_registers_block(block, &state);
|
|
}
|
|
|
|
nir_foreach_block(block, impl) {
|
|
resolve_parallel_copies_block(block, &state);
|
|
}
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_block_index |
|
|
nir_metadata_dominance);
|
|
|
|
/* Clean up dead instructions and the hash tables */
|
|
nir_instr_free_list(&state.dead_instrs);
|
|
_mesa_hash_table_destroy(state.merge_node_table, NULL);
|
|
ralloc_free(state.dead_ctx);
|
|
return state.progress;
|
|
}
|
|
|
|
bool
|
|
nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only)
|
|
{
|
|
bool progress = false;
|
|
|
|
nir_foreach_function(function, shader) {
|
|
if (function->impl)
|
|
progress |= nir_convert_from_ssa_impl(function->impl, phi_webs_only);
|
|
}
|
|
|
|
return progress;
|
|
}
|
|
|
|
|
|
static void
|
|
place_phi_read(nir_builder *b, nir_register *reg,
|
|
nir_ssa_def *def, nir_block *block, struct set *visited_blocks)
|
|
{
|
|
/* Search already visited blocks to avoid back edges in tree */
|
|
if (_mesa_set_search(visited_blocks, block) == NULL) {
|
|
/* Try to go up the single-successor tree */
|
|
bool all_single_successors = true;
|
|
set_foreach(block->predecessors, entry) {
|
|
nir_block *pred = (nir_block *)entry->key;
|
|
if (pred->successors[0] && pred->successors[1]) {
|
|
all_single_successors = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (all_single_successors) {
|
|
/* All predecessors of this block have exactly one successor and it
|
|
* is this block so they must eventually lead here without
|
|
* intersecting each other. Place the reads in the predecessors
|
|
* instead of this block.
|
|
*/
|
|
_mesa_set_add(visited_blocks, block);
|
|
|
|
set_foreach(block->predecessors, entry) {
|
|
place_phi_read(b, reg, def, (nir_block *)entry->key, visited_blocks);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
b->cursor = nir_after_block_before_jump(block);
|
|
nir_store_reg(b, reg, def, ~0);
|
|
}
|
|
|
|
/** Lower all of the phi nodes in a block to movs to and from a register
|
|
*
|
|
* This provides a very quick-and-dirty out-of-SSA pass that you can run on a
|
|
* single block to convert all of its phis to a register and some movs.
|
|
* The code that is generated, while not optimal for actual codegen in a
|
|
* back-end, is easy to generate, correct, and will turn into the same set of
|
|
* phis after you call regs_to_ssa and do some copy propagation. For each phi
|
|
* node we do the following:
|
|
*
|
|
* 1. For each phi instruction in the block, create a new nir_register
|
|
*
|
|
* 2. Insert movs at the top of the destination block for each phi and
|
|
* rewrite all uses of the phi to use the mov.
|
|
*
|
|
* 3. For each phi source, insert movs in the predecessor block from the phi
|
|
* source to the register associated with the phi.
|
|
*
|
|
* Correctness is guaranteed by the fact that we create a new register for
|
|
* each phi and emit movs on both sides of the control-flow edge. Because all
|
|
* the phis have SSA destinations (we assert this) and there is a separate
|
|
* temporary for each phi, all movs inserted in any particular block have
|
|
* unique destinations so the order of operations does not matter.
|
|
*
|
|
* The one intelligent thing this pass does is that it places the moves from
|
|
* the phi sources as high up the predecessor tree as possible instead of in
|
|
* the exact predecessor. This means that, in particular, it will crawl into
|
|
* the deepest nesting of any if-ladders. In order to ensure that doing so is
|
|
* safe, it stops as soon as one of the predecessors has multiple successors.
|
|
*/
|
|
bool
|
|
nir_lower_phis_to_regs_block(nir_block *block)
|
|
{
|
|
nir_builder b;
|
|
nir_builder_init(&b, nir_cf_node_get_function(&block->cf_node));
|
|
struct set *visited_blocks = _mesa_set_create(NULL, _mesa_hash_pointer,
|
|
_mesa_key_pointer_equal);
|
|
|
|
bool progress = false;
|
|
nir_foreach_instr_safe(instr, block) {
|
|
if (instr->type != nir_instr_type_phi)
|
|
break;
|
|
|
|
nir_phi_instr *phi = nir_instr_as_phi(instr);
|
|
assert(phi->dest.is_ssa);
|
|
|
|
nir_register *reg = create_reg_for_ssa_def(&phi->dest.ssa, b.impl);
|
|
|
|
b.cursor = nir_after_instr(&phi->instr);
|
|
nir_ssa_def *def = nir_load_reg(&b, reg);
|
|
|
|
nir_ssa_def_rewrite_uses(&phi->dest.ssa, def);
|
|
|
|
nir_foreach_phi_src(src, phi) {
|
|
if (src->src.is_ssa) {
|
|
_mesa_set_add(visited_blocks, src->src.ssa->parent_instr->block);
|
|
place_phi_read(&b, reg, src->src.ssa, src->pred, visited_blocks);
|
|
_mesa_set_clear(visited_blocks, NULL);
|
|
} else {
|
|
b.cursor = nir_after_block_before_jump(src->pred);
|
|
nir_ssa_def *src_ssa =
|
|
nir_ssa_for_src(&b, src->src, phi->dest.ssa.num_components);
|
|
nir_store_reg(&b, reg, src_ssa, ~0);
|
|
}
|
|
}
|
|
|
|
nir_instr_remove(&phi->instr);
|
|
|
|
progress = true;
|
|
}
|
|
|
|
_mesa_set_destroy(visited_blocks, NULL);
|
|
|
|
return progress;
|
|
}
|
|
|
|
struct ssa_def_to_reg_state {
|
|
nir_function_impl *impl;
|
|
bool progress;
|
|
};
|
|
|
|
static bool
|
|
dest_replace_ssa_with_reg(nir_dest *dest, void *void_state)
|
|
{
|
|
struct ssa_def_to_reg_state *state = void_state;
|
|
|
|
if (!dest->is_ssa)
|
|
return true;
|
|
|
|
nir_register *reg = create_reg_for_ssa_def(&dest->ssa, state->impl);
|
|
|
|
nir_ssa_def_rewrite_uses_src(&dest->ssa, nir_src_for_reg(reg));
|
|
|
|
nir_instr *instr = dest->ssa.parent_instr;
|
|
*dest = nir_dest_for_reg(reg);
|
|
dest->reg.parent_instr = instr;
|
|
list_addtail(&dest->reg.def_link, ®->defs);
|
|
|
|
state->progress = true;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
ssa_def_is_local_to_block(nir_ssa_def *def, UNUSED void *state)
|
|
{
|
|
nir_block *block = def->parent_instr->block;
|
|
nir_foreach_use(use_src, def) {
|
|
if (use_src->parent_instr->block != block ||
|
|
use_src->parent_instr->type == nir_instr_type_phi) {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (!list_is_empty(&def->if_uses))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
/** Lower all of the SSA defs in a block to registers
|
|
*
|
|
* This performs the very simple operation of blindly replacing all of the SSA
|
|
* defs in the given block with registers. If not used carefully, this may
|
|
* result in phi nodes with register sources which is technically invalid.
|
|
* Fortunately, the register-based into-SSA pass handles them anyway.
|
|
*/
|
|
bool
|
|
nir_lower_ssa_defs_to_regs_block(nir_block *block)
|
|
{
|
|
nir_function_impl *impl = nir_cf_node_get_function(&block->cf_node);
|
|
nir_shader *shader = impl->function->shader;
|
|
|
|
struct ssa_def_to_reg_state state = {
|
|
.impl = impl,
|
|
.progress = false,
|
|
};
|
|
|
|
nir_foreach_instr(instr, block) {
|
|
if (instr->type == nir_instr_type_ssa_undef) {
|
|
/* Undefs are just a read of something never written. */
|
|
nir_ssa_undef_instr *undef = nir_instr_as_ssa_undef(instr);
|
|
nir_register *reg = create_reg_for_ssa_def(&undef->def, state.impl);
|
|
nir_ssa_def_rewrite_uses_src(&undef->def, nir_src_for_reg(reg));
|
|
} else if (instr->type == nir_instr_type_load_const) {
|
|
/* Constant loads are SSA-only, we need to insert a move */
|
|
nir_load_const_instr *load = nir_instr_as_load_const(instr);
|
|
nir_register *reg = create_reg_for_ssa_def(&load->def, state.impl);
|
|
nir_ssa_def_rewrite_uses_src(&load->def, nir_src_for_reg(reg));
|
|
|
|
nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
|
|
mov->src[0].src = nir_src_for_ssa(&load->def);
|
|
mov->dest.dest = nir_dest_for_reg(reg);
|
|
mov->dest.write_mask = (1 << reg->num_components) - 1;
|
|
nir_instr_insert(nir_after_instr(&load->instr), &mov->instr);
|
|
} else if (nir_foreach_ssa_def(instr, ssa_def_is_local_to_block, NULL)) {
|
|
/* If the SSA def produced by this instruction is only in the block
|
|
* in which it is defined and is not used by ifs or phis, then we
|
|
* don't have a reason to convert it to a register.
|
|
*/
|
|
} else {
|
|
nir_foreach_dest(instr, dest_replace_ssa_with_reg, &state);
|
|
}
|
|
}
|
|
|
|
return state.progress;
|
|
}
|