Commit Graph

91020 Commits

Author SHA1 Message Date
Tim Rowley af909c0200 swr: [rasterizer jitter] Remove HAVE_LLVM tests supporting llvm < 3.8
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley 973d38801d swr: [rasterizer common/core] Fix 32-bit windows build
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley 217b791a44 swr: [rasterizer core] Fix unused variable warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley da7aa39f93 swr: [rasterizer core] Code formating change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley c8cc07ca25 swr: [rasterizer core] SIMD16 Frontend WIP - PA
Fix PA NextPrim for SIMD8 on SIMD16.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley 08a7136848 swr: [rasterizer core] SIMD16 Frontend WIP - Clipper
Implement widened clipper for SIMD16.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley 0033e86b2c swr: [rasterizer core] Multisample sample position setup change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Tim Rowley 4c093869db swr: [rasterizer core] Reduce templates to speed compile
Quick patch to remove some unused template params to cut down
rasterizer compile time.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-11 18:01:03 -05:00
Francisco Jerez 147e71242c i965/fs: Take into account lower frequency of conditional blocks in spilling cost heuristic.
The individual branches of an if/else/endif construct will be executed
some unknown number of times between 0 and 1 relative to the parent
block.  Use some factor in between as weight while approximating the
cost of spill/fill instructions within a conditional if-else branch.
This favors spilling registers used within conditional branches which
are likely to be executed less frequently than registers used at the
top level.

Improves the framerate of the SynMark2 OglCSDof benchmark by ~1.9x on
my SKL GT4e.  Should have a comparable effect on other platforms.  No
significant regressions.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-11 15:28:54 -07:00
Tim Rowley 9a7b257450 swr: return true for PIPE_CAP_DOUBLES
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-04-11 13:16:43 -05:00
Kenneth Graunke 02ccd8f52c i965: Set kernel features before computing max GL version.
We check these bitfields when computing the Haswell max GL version.
We need to set them ahead of time, or they won't exist, and all our
checks will fail.  That sets the max core profile GL version to 4.2.

This introduces the bizarre situation where asking for a GL context
with version 4.3+ fails, but asking for a GL core profile context
with version <= 4.2 actually promotes you a 4.5 context.

GLX_MESA_query_renderer also reported the bogus 4.2 value.
Now it shows 4.5.

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reported-and-tested-by: Rafael Ristovski <rafael.ristovski@gmail.com>
2017-04-11 08:58:16 -07:00
Juan A. Suarez Romero 8d7a82ae32 anv: remove needless VALGRIND_MAKE_MEM_DEFINED
This is already invoked in the following VG_NOACCESS_READ() call.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-11 17:21:57 +02:00
Lucas Stach 4ee7c2c284 etnaviv: enable TS, but disable autodisable
Autodisable seems to cause missed rendering in some cases, but
otherwise TS seems to work properly.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-04-11 16:52:31 +02:00
Lucas Stach 797890bbbd etnaviv: enable TS also on sampler resources
Fixes a performance issue with imported winsys buffers as those are
marked with binding sampler view.

This might require a TS flush on single pipe chips that directly
sample from the rendered buffer, but otherwise seems to work fine.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-04-11 16:52:27 +02:00
Lucas Stach 52f6c8cc31 etnaviv: align TS surface size to number of pixel pipes
The TS surface gets cleared by a tiled RS fill. If the chip has
more than 1 pixel pipe the size of the TS surface needs to be
aligned so that each pipe address matches a tile start, otherwise
the RS will hang.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-04-11 16:52:22 +02:00
Lucas Stach 37622ecc79 etnaviv: avoid using invalid TS
The TS is only valid after it has been initialized by a fast
clear, so it should not be taken into account when blitting
resources that haven't been cleared. Also the blit itself
invalidates the destination TS, as it's not updated and will
retain data from the previous rendering after the blit.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-04-11 16:52:01 +02:00
Samuel Pitoiset 768f81b62b glsl: use the BA1 macro for textureQueryLevels()
For both consistency and new bindless sampler types.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-04-11 10:24:57 +02:00
Samuel Pitoiset 981ba1c89b glsl: use the BA1 macro for textureSamples()
For both consistency and new bindless sampler types.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-04-11 10:24:54 +02:00
Samuel Pitoiset 29082b0b22 glsl: use the BA1 macro for textureCubeArrayShadow()
For both consistency and new bindless sampler types.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-04-11 10:24:51 +02:00
Bas Nieuwenhuizen 8475a14302 radv: Implement pipeline statistics queries.
The devil is in the shader again, otherwise this is
fairly straightforward.

The CTS contains no pipeline statistics copy to buffer
testcases, so I did a basic smoketest.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Bas Nieuwenhuizen d2906bc72d radv: Let count be dynamic in radv_break_on_count.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Bas Nieuwenhuizen 8473193760 radv: Rename query pipeline/set layout.
For using them with both occlusion and pipeline statistics queries.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Bas Nieuwenhuizen 95743d5b88 radv: Use VK_WHOLE_SIZE for the query buffer bindings.
The buffer sizes are specified just a few lines earlier, so don't
repeat ourselves.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Bas Nieuwenhuizen 8911dd6d12 radv: Use a shader for occlusion CmdCopyQueryPoolResults.
Use the new occlusion query copy shader.

We don't use the shader for the waiting as a polling loop ineracts badly
with having caching enabled. I noticed on my GPU (Tonga) that the values
are written out in order, so I just use a WAIT_REG_MEM on the last value.

If it turns out other chips don't do that we may need to look a bit more
into this. Having 8 WAIT_REG_MEM packets per query doesn't sound ideal.

This also restricts the availability word in the pool to timestamp queries
only, as occlusion queries don't use it, and pipeline statistic queries
likely won't either.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Bas Nieuwenhuizen ce0c8cf941 radv: Add occlusion query shader.
Adds a shader for writing occlusion query results to a buffer, as the
CP packet isn't support on SI or secondary buffers, and doesn't handle
the availability bit (or partial results) nor truncation to 32-bit.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-11 09:33:17 +02:00
Kenneth Graunke 50b987c0f0 i965: Fix wonky indentation left by brw_bo_alloc_tiled rename. 2017-04-10 23:25:13 -07:00
Ilia Mirkin d9cc58d6ec nouveau: when mapping a persistent buffer, synchronize on former xfers
If the buffer is being used, we should wait for those uses to be
complete before returning the map.

Fixes: GL45-CTS.direct_state_access.buffers_functional
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-04-11 00:13:55 -04:00
Ilia Mirkin 8036809799 nvc0: increase texture buffer object alignment to 256 for pre-GM107
We currently don't pass the low byte of the address via the surface
info, so in order to work with images, these have to implicitly be
aligned to 256. The proprietary driver also doesn't go out of its way to
provide lower alignment.

Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-11 00:13:55 -04:00
Timothy Arceri 8ffd54fef8 mesa: fix typo and add assert() to _mesa_attach_renderbuffer_without_ref()
This function should only be used with a "freshly created" renderbuffer
so assert RefCount is 1.
2017-04-11 09:57:45 +10:00
Kenneth Graunke bd84252be6 i965/drm: Add stall warnings when mapping or waiting on BOs.
This restores the performance warnings removed in:

    i965: Drop brw_bo_map[_gtt] wrappers which issue perf warnings.

but adds them for nearly all BO mapping, and also for wait_rendering.

Because we add this to the core bufmgr, we automatically get stall
warnings in all callers, unlike before where only a few callsites used
the wrappers that gave stall warnings.

We also do it a bit differently: we simply measure how long set_domain
takes (the part that stalls), and complain if it's more than 0.01 ms.
We don't bother calling brw_bo_busy(), and we don't measure the mmap
time (which doesn't stall).  This should be more accurate.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-04-10 14:33:18 -07:00
Kenneth Graunke f053ee78ed i965/drm: Make a set_domain() helper function.
Less boilerplate.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-04-10 14:33:18 -07:00
Daniel Vetter a99a4979fd i965/batch: Ensure we use a consistent offset in relocs
In theory gcc is free to re-load them, and if a concurrent
execbuf races and updates bo->offset64 then we have a problem:
execbuffer api requires that the ->presumed_offset and the one
we used for the reloc matches. It does not require that the value
is sensible, which means no locks needed, just a consistent load.

Ken said his next series will nuke this, so just hand-roll the
kernel's READ_ONCE idea inline.

FIXME: Most callers of brw_emit_reloc recompute the relocation
themselves, which means this doesn't really fix the race. But the long
term plan is to move to per-context relocation handling, which will
fix this all properly. So leave this for now as just a reminder.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:18 -07:00
Daniel Vetter 7f3c85c21e i965/bufmgr: Garbage-collect vma cache/pruning
This was done because the kernel has 1 global address space, shared
with all render clients, for gtt mmap offsets, and that address space
was only 32bit on 32bit kernels.

This was fixed  in

commit 440fd5283a87345cdd4237bdf45fb01130ea0056
Author: Thierry Reding <treding@nvidia.com>
Date:   Fri Jan 23 09:05:06 2015 +0100

    drm/mm: Support 4 GiB and larger ranges

which shipped in 4.0. Of course you still want to limit the bo cache
to a reasonable size on 32bit apps to avoid ENOMEM, but that's better
solved by tuning the cache a bit. On 64bit, this was never an issue.

On top, mesa never set this, so it's all dead code. Collect an trash it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:18 -07:00
Daniel Vetter 1f965d3f7a i965/bufmgr: Remove some reuse functions
is_reusable was needed by uxa because it couldn't keep track of its
scanout buffers and used this as a proxy. Disabling reuse is a silly
idea, we set this once at start. Remove both.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:18 -07:00
Daniel Vetter edd85c1f04 i965/bufmgr: remove start_gtt_access
Iirc this was used by uxa for persistent mmpas of the frontbuffer. For
mesa all the set_domain stuff needed before a synchronized mmap is handled
within the bufmgr, so no reason ever to call this.

Inline the implementation into its only internal user.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:17 -07:00
Daniel Vetter 439edaa4b5 i965/bufmgr: Delete set_tiling
Entirely unused, and really shouldn't be used. The alloc functions already
take care of this. And even in a future where we're not going to
h/v-align tiled buffers in the bufmgr, but only in isl, I think we
still want to adjust the tiling mode in the bufmgr, since that ties in
closely to mmaps and stuff like that.

get_tiling is still needed for the import paths (until we have modifiers
everywhere).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:17 -07:00
Daniel Vetter 6308121475 i965/bufmgr: Delete alloc_for_render
Entirely unused, mesa instead used the BO_ALLOC_FOR_RENDER flag.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-10 14:33:14 -07:00
Kenneth Graunke 538fa87f40 i965/drm: Use list_for_each_entry_safe in a couple of cases.
Suggested by Chris Wilson.  A tiny bit simpler.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-04-10 14:33:12 -07:00
Kenneth Graunke 10929da5fb i965/drm: Rename intel_bufmgr_gem.c to brw_bufmgr.c.
Matches the class name and the header file name.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:32 -07:00
Kenneth Graunke 7aa66e64fe i965/drm: Reindent intel_bufmgr_gem.c and brw_bufmgr.h.
indent -i3 -nut -br -brs -npcs -ce --no-tabs -Tuint32_t -Tuint64_t
plus some manual fixes because those aren't quite the right settings.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:30 -07:00
Kenneth Graunke d30a92738c i965/drm: Rename drm_bacon_bo to brw_bo.
The bacon is all gone.

This renames both the class and the related functions.  We're about to
run indent on the bufmgr code, so no need to worry about fixing bad
indentation.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:28 -07:00
Kenneth Graunke e0d15e9769 i965: Drop brw_bo_map[_gtt] wrappers which issue perf warnings.
The stupid reason for eliminating these functions is that I'm about
to rename drm_bacon_bo_map() to brw_bo_map(), which makes the real
function have the short name, rather than the wrapper.

I'm also planning on reworking our mapping code soon, so we use WC
mappings and proper unsynchronized mappings on non-LLC platforms.
It will be easier to do that without thinking about the stall
warnings and wrappers.

My eventual hope is to put the performance warnings in the BO map
function itself, so all callers gain the warning.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:25 -07:00
Kenneth Graunke dfd81373b6 i965/drm: Rename drm_bacon_reg_read() to brw_reg_read().
Less bacon.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:24 -07:00
Kenneth Graunke 662a733dbc i965/drm: Rename drm_bacon_bufmgr to struct brw_bufmgr.
Also stop using typedefs, per Mesa coding style.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:21 -07:00
Kenneth Graunke f5216b25e0 i965: Just use a uint32_t context handle rather than a malloc'd wrapper.
drm_bacon_context is a malloc'd struct containing a uint32_t context ID
and a pointer back to the bufmgr.  The bufmgr pointer is pretty useless,
as everybody already has brw->bufmgr.  At that point...we may as well
just use the ctx_id handle directly.  A number of places already had to
call drm_bacon_gem_context_get_id() to extract the ID anyway.  Now they
just have it.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:20 -07:00
Kenneth Graunke 4cb3e4429d i965/drm: Fold drm_bacon_gem_reset_stats into the callers.
We're going to get rid of drm_bacon_context shortly, so we'd have to
change the interface slightly.  It's basically just an ioctl wrapper
that isn't terribly bufmgr-related, so We may as well just combine it
with the code in brw_reset.c that actually uses it.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:19 -07:00
Kenneth Graunke 414c9343a2 i965/drm: Rename drm_bacon_gem_bo_bucket to bo_cache_bucket.
No need for a prefix as this struct is local to the .c file.

Less bacon.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:17 -07:00
Kenneth Graunke e46b74d1b5 i965/drm: Drop drm_bacon_* from static functions.
Mesa style is to not use lengthy prefixes for static functions.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:16 -07:00
Kenneth Graunke 13596ecb6b i965/drm: Drop drm_bacon_gem_bo_madvise_internal().
The only difference is that it takes an explicit bufmgr rather than
using bo->bufmgr, but there is only one bufmgr per screen so they
should be identical anyway.

Chris says this was added primarly to avoid bo/bo_gem casting,
which was inconvenient.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:15 -07:00
Kenneth Graunke 9ee252865e i965/drm: Merge drm_bacon_bo_gem into drm_bacon_bo.
The separate class gives us a bit of extra encapsulation, but I don't
know that it's really worth the boilerplate.  I think we can reasonably
expect the rest of the driver to be responsible.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-10 14:32:14 -07:00