Commit Graph

90507 Commits

Author SHA1 Message Date
Nicolai Hähnle 7f160efcde amd/addrlib: import gfx9 support 2017-03-30 14:44:33 +02:00
Kevin Furrow 047d6daf10 amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to differentiate between 64 and 128bpp formats. 2017-03-30 14:44:33 +02:00
Kevin Furrow 1360018c1c amd/addrlib: Fix selection of swizzle modes for 3D compressed images. 2017-03-30 14:44:33 +02:00
Kevin Furrow 9705e3b72c amd/addrlib: Add support for ETC2 and ASTC formats. 2017-03-30 14:44:33 +02:00
Joe Ma a489cdb20f amd/addrlib: Bump version to 6.02 2017-03-30 14:44:33 +02:00
Frans Gu e736edf63d amd/addrlib: Adjust slie size after pitch and actual height adjustment 2017-03-30 14:44:33 +02:00
Frans Gu 588e5bbf3d amd/addrlib: Apply input pitch after internal pitch aligning 2017-03-30 14:44:33 +02:00
Nicolai Hähnle 11f1306207 amdgpu/addrlib: Bump version to 6.01
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle a136926eef amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 48bf5d0800 amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly 2017-03-30 14:44:33 +02:00
Nicolai Hähnle 33c25655c1 amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI
If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.
2017-03-30 14:44:33 +02:00
Xavi Zhang fa906a888b amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes
The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.

1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.

Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.
2017-03-30 14:44:33 +02:00
Frans Gu 6764d96eaa amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings
By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.
2017-03-30 14:44:33 +02:00
Frans Gu ed1aca8e8f amdgpu/addrlib: do some tile mode conversions to display surface 2017-03-30 14:44:33 +02:00
Xavi Zhang cb8844392c amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC. 2017-03-30 14:44:33 +02:00
Frans Gu fe216415c6 amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.

Also, related changes to tile mode optimization for needEquation.
2017-03-30 14:44:33 +02:00
Xavi Zhang 4dd4700612 amdgpu/addrlib: Always returns pixelPitch in original pixels 2017-03-30 14:44:33 +02:00
Sabre Shao eb3036ed46 amdgpu/addrlib: fix crash on allocation failure 2017-03-30 14:44:33 +02:00
Frans Gu 680f91e5d4 amdgpu/addrlib: Add flag to report if a surface can have dcc ram 2017-03-30 14:44:33 +02:00
Roy Zhan ca88f83222 amdgpu/addrlib: support non-power2 height alignment (for linear surface) 2017-03-30 14:44:33 +02:00
Frans Gu c867a2b222 amdgpu/addrlib: Fix family setting for VI and CZ ASICs 2017-03-30 14:44:33 +02:00
Nicolai Hähnle b328e47d3d amdgpu/addrlib: style cleanup
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle fbc9ba7559 amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
2017-03-30 14:44:33 +02:00
Xavi Zhang 145750efba amdgpu/addrlib: Fix number of //
Find ^/{80,99}$  and replace them to 100 "/"

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 4e2668ecd1 amdgpu/addrlib: Cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang d1ecb70ba3 amdgpu/addrlib: Use namespaces
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Kevin Zhao 8912862a40 amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Frans Gu acaeae2861 amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
2017-03-30 14:44:33 +02:00
Xavi Zhang 90029b958e amdgpu/addrlib: Stylish cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Roy Zhan 554c1b9f2d amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled
Experiment show 1D tiling + TcCompatible cannot work together.
2017-03-30 14:44:33 +02:00
Xavi Zhang 120a5d0e42 amdgpu/addrlib: fix pixel index calculation of thick micro tiling 2017-03-30 14:44:33 +02:00
Xavi Zhang 199912a9bc amdgpu/addrlib: Add a flag to skip calculate indices
This is useful for debugging and special cases for stencil surfaces
do not require texture fetch compatible.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 10f7d1cb03 amdgpu/addrlib: add equation generation
1. Add new surface flags needEquation for client driver use to force
the surface tile setting equation compatible. Override 2D/3D macro
tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1.
2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure
to return number of equations and the equation table to client driver
3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to
return the equation index to client driver

Please note the use of address equation has following restrictions:
1) The surface can't be splitable
2) The surface can't have non zero tile swizzle value
3) Surface with > 1 slices must have PRT tile mode, which disable
slice rotation
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 3e44337bd6 amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness 2017-03-30 14:44:33 +02:00
Xavi Zhang 79dcda5116 amdgpu/addrlib: add define HAVE_TSERVER 2017-03-30 14:44:33 +02:00
Frans Gu 7293a020bd amdgpu/addrlib: Add new interface to support macro mode index query 2017-03-30 14:44:33 +02:00
Roy Zhan c16e1e2041 amdgpu/addrlib: add explicit Log2NonPow2 function 2017-03-30 14:44:33 +02:00
Nicolai Hähnle 4a4b7da141 amdgpu/addrlib: Fix invalid access to m_tileTable
Sometimes client driver passes valid tile info into address library,
in this case, the tile index is computed in function
HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg.
We need to call HwlPostCheckTileIndex to calculate the correct tile
index to get tile split bytes for this case.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 9e40e09089 amdgpu/addrlib: add ADDR_ANALYSIS_ASSUME
It helps fix analysis warnings in MSC.
2017-03-30 14:44:33 +02:00
XiaoYuan Zheng 6164f23a91 amdgpu/addrlib: add tcCompatible htile addr from coordinate support. 2017-03-30 14:44:33 +02:00
Carlos Xiong 3bd1380ab2 amdgpu/addrlib: force all zero tile info for linear general. 2017-03-30 14:44:33 +02:00
Nicolai Hähnle 8b110f0319 amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW
When clients queries tile Info from tile index and expects accurate
tileSplit info,  bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.
2017-03-30 14:44:33 +02:00
Frans Gu ca6a38fd6a amdgpu/addrlib: Refine the PRT tile mode selection
Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.
2017-03-30 14:44:33 +02:00
Xavi Zhang 2bf243f7c6 amdgpu/addrlib: add dccRamSizeAligned output flag
This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle e443b48966 amdgpu/addrlib: Change comment alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle e06aeaf19f amdgpu/addrlib: style changes and minor cleanups
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle cb5d22a3f3 amdgpu/addrlib: AddrLib inheritance refactor
Add one more abstraction layer into inheritance system.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle 52a1288a15 amdgpu/addrlib: rearrange code in preparation of refactoring
No code changes.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang f12d430c59 amdgpu/addrlib: add disableLinearOpt flag 2017-03-30 14:44:33 +02:00
Xavi Zhang b5d8120a07 amdgpu/addrlib: Add GetMaxAlignments 2017-03-30 14:44:33 +02:00