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amdgpu/addrlib: add dccRamSizeAligned output flag 

This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
This commit is contained in:
Xavi Zhang 2014-11-24 22:49:50 -05:00 committed by Marek Olšák
parent e443b48966
commit 2bf243f7c6
2 changed files with 7 additions and 1 deletions
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3
src/amd/addrlib/addrinterface.h
View File

@ -2128,7 +2128,8 @@ typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key
UINT_64 dccRamSize; ///< Size of dcc key
UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
BOOL_32 subLvlCompressible; ///< whether sub resource is compressiable
BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
} ADDR_COMPUTE_DCCINFO_OUTPUT;
/**

5
src/amd/addrlib/r800/ciaddrlib.cpp
View File

@ -247,6 +247,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
HwlGetPipes(&pIn->tileInfo) *
m_pipeInterleaveBytes;
pOut->dccFastClearSize = dccFastClearSize;
pOut->dccRamSizeAligned = TRUE;
ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
@ -262,6 +263,10 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
{
pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
}
if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
{
pOut->dccRamSizeAligned = FALSE;
}
pOut->dccRamSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
pOut->subLvlCompressible = FALSE;
}