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amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign 

1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.

Also, related changes to tile mode optimization for needEquation.
This commit is contained in:
Frans Gu 2015-08-17 23:56:23 -04:00 committed by Marek Olšák
parent 4dd4700612
commit fe216415c6
9 changed files with 403 additions and 159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/amd/addrlib/addrinterface.h
View File

@ -515,7 +515,8 @@ typedef union _ADDR_SURFACE_FLAGS
/// which is needed by swizzle pattern equation.
UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.
UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
UINT_32 reserved : 6; ///< Reserved bits
UINT_32 minimizeAlignment : 1; ///< Minimize alignment
UINT_32 reserved : 5; ///< Reserved bits
};
UINT_32 value;
@ -557,6 +558,9 @@ typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a
/// must for mip levels from SI+.
/// Don't use pitch in blocks for compressed formats!
UINT_32 maxBaseAlign; ///< Max base alignment request from client
UINT_32 pitchAlign; ///< Pitch alignment request from client
UINT_32 heightAlign; ///< Height alignment request from client
} ADDR_COMPUTE_SURFACE_INFO_INPUT;
/**

209
src/amd/addrlib/core/addrlib1.cpp
View File

@ -346,13 +346,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
// HWL layer may override tile mode if necessary
HwlOverrideTileMode(&localIn);
AddrTileMode tileMode = localIn.tileMode;
// Optimize tile mode if possible
if (OptimizeTileMode(&localIn, &tileMode))
{
localIn.tileMode = tileMode;
}
OptimizeTileMode(&localIn);
}
}
@ -3508,6 +3503,45 @@ VOID Lib::ComputeMipLevel(
HwlComputeMipLevel(pIn);
}
/**
****************************************************************************************************
* Lib::DegradeTo1D
*
* @brief
* Check if surface can be degraded to 1D
* @return
* TRUE if degraded
****************************************************************************************************
*/
BOOL_32 Lib::DegradeTo1D(
UINT_32 width, ///< surface width
UINT_32 height, ///< surface height
UINT_32 macroTilePitchAlign, ///< macro tile pitch align
UINT_32 macroTileHeightAlign ///< macro tile height align
)
{
BOOL_32 degrade = ((width < macroTilePitchAlign) || (height < macroTileHeightAlign));
// Check whether 2D tiling still has too much footprint
if (degrade == FALSE)
{
// Only check width and height as slices are aligned to thickness
UINT_64 unalignedSize = width * height;
UINT_32 alignedPitch = PowTwoAlign(width, macroTilePitchAlign);
UINT_32 alignedHeight = PowTwoAlign(height, macroTileHeightAlign);
UINT_64 alignedSize = alignedPitch * alignedHeight;
// alignedSize > 1.5 * unalignedSize
if (2 * alignedSize > 3 * unalignedSize)
{
degrade = TRUE;
}
}
return degrade;
}
/**
****************************************************************************************************
* Lib::OptimizeTileMode
@ -3515,67 +3549,148 @@ VOID Lib::ComputeMipLevel(
* @brief
* Check if base level's tile mode can be optimized (degraded)
* @return
* TRUE if degraded, also returns degraded tile mode (unchanged if not degraded)
* N/A
****************************************************************************************************
*/
BOOL_32 Lib::OptimizeTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure for surface info
AddrTileMode* pTileMode ///< [out] Degraded tile mode
VOID Lib::OptimizeTileMode(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in, out] structure for surface info
) const
{
AddrTileMode tileMode = pIn->tileMode;
UINT_32 thickness = Thickness(tileMode);
AddrTileMode tileMode = pInOut->tileMode;
BOOL_32 doOpt = (pInOut->flags.opt4Space == TRUE) ||
(pInOut->flags.minimizeAlignment == TRUE) ||
(pInOut->maxBaseAlign != 0);
// Optimization can only be done on level 0 and samples <= 1
if ((pIn->flags.opt4Space == TRUE) &&
(pIn->mipLevel == 0) &&
(pIn->numSamples <= 1) &&
(pIn->flags.display == FALSE) &&
if ((doOpt == TRUE) &&
(pInOut->mipLevel == 0) &&
(pInOut->flags.display == FALSE) &&
(IsPrtTileMode(tileMode) == FALSE) &&
(pIn->flags.prt == FALSE))
(pInOut->flags.prt == FALSE))
{
// Check if linear mode is optimal
if ((pIn->height == 1) &&
(IsLinear(tileMode) == FALSE) &&
(ElemLib::IsBlockCompressed(pIn->format) == FALSE) &&
(pIn->flags.depth == FALSE) &&
(pIn->flags.stencil == FALSE) &&
(m_configFlags.disableLinearOpt == FALSE) &&
(pIn->flags.disableLinearOpt == FALSE))
UINT_32 width = pInOut->width;
UINT_32 height = pInOut->height;
UINT_32 thickness = Thickness(tileMode);
BOOL_32 convertToPrt = FALSE;
BOOL_32 macroTiledOK = TRUE;
UINT_32 macroWidthAlign = 0;
UINT_32 macroHeightAlign = 0;
UINT_32 macroSizeAlign = 0;
if (IsMacroTiled(tileMode))
{
tileMode = ADDR_TM_LINEAR_ALIGNED;
macroTiledOK = HwlGetAlignmentInfoMacroTiled(pInOut,
&macroWidthAlign,
&macroHeightAlign,
&macroSizeAlign);
}
else if (IsMacroTiled(tileMode))
if (macroTiledOK)
{
if (HwlDegradeBaseLevel(pIn))
if ((pInOut->flags.opt4Space == TRUE) && (pInOut->numSamples <= 1))
{
tileMode = (thickness == 1) ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
}
else if (thickness > 1)
{
// As in the following HwlComputeSurfaceInfo, thick modes may be degraded to
// thinner modes, we should re-evaluate whether the corresponding thinner modes
// need to be degraded. If so, we choose 1D thick mode instead.
tileMode = DegradeLargeThickTile(pIn->tileMode, pIn->bpp);
if (tileMode != pIn->tileMode)
// Check if linear mode is optimal
if ((pInOut->height == 1) &&
(IsLinear(tileMode) == FALSE) &&
(ElemLib::IsBlockCompressed(pInOut->format) == FALSE) &&
(pInOut->flags.depth == FALSE) &&
(pInOut->flags.stencil == FALSE) &&
(m_configFlags.disableLinearOpt == FALSE) &&
(pInOut->flags.disableLinearOpt == FALSE))
{
ADDR_COMPUTE_SURFACE_INFO_INPUT input = *pIn;
input.tileMode = tileMode;
if (HwlDegradeBaseLevel(&input))
tileMode = ADDR_TM_LINEAR_ALIGNED;
}
else if (IsMacroTiled(tileMode))
{
if (DegradeTo1D(width, height, macroWidthAlign, macroHeightAlign))
{
tileMode = ADDR_TM_1D_TILED_THICK;
tileMode = (thickness == 1) ?
ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
}
else if (thickness > 1)
{
// As in the following HwlComputeSurfaceInfo, thick modes may be degraded to
// thinner modes, we should re-evaluate whether the corresponding
// thinner modes should be degraded. If so, we choose 1D thick mode instead.
tileMode = DegradeLargeThickTile(pInOut->tileMode, pInOut->bpp);
if (tileMode != pInOut->tileMode)
{
// Get thickness again after large thick degrade
thickness = Thickness(tileMode);
ADDR_COMPUTE_SURFACE_INFO_INPUT input = *pInOut;
input.tileMode = tileMode;
macroTiledOK = HwlGetAlignmentInfoMacroTiled(&input,
&macroWidthAlign,
&macroHeightAlign,
&macroSizeAlign);
if (macroTiledOK &&
DegradeTo1D(width, height, macroWidthAlign, macroHeightAlign))
{
tileMode = ADDR_TM_1D_TILED_THICK;
}
}
}
}
}
if (macroTiledOK)
{
if ((pInOut->flags.minimizeAlignment == TRUE) &&
(pInOut->numSamples <= 1) &&
(IsMacroTiled(tileMode) == TRUE))
{
UINT_32 macroSize = PowTwoAlign(width, macroWidthAlign) *
PowTwoAlign(height, macroHeightAlign);
UINT_32 microSize = PowTwoAlign(width, MicroTileWidth) *
PowTwoAlign(height, MicroTileHeight);
if (macroSize > microSize)
{
tileMode = (thickness == 1) ?
ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
}
}
if ((pInOut->maxBaseAlign != 0) &&
(IsMacroTiled(tileMode) == TRUE))
{
if (macroSizeAlign > pInOut->maxBaseAlign)
{
if (pInOut->numSamples > 1)
{
ADDR_ASSERT(pInOut->maxBaseAlign >= Block64K);
convertToPrt = TRUE;
}
else if (pInOut->maxBaseAlign < Block64K)
{
tileMode = (thickness == 1) ?
ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
}
else
{
convertToPrt = TRUE;
}
}
}
}
}
if (convertToPrt)
{
HwlSetPrtTileMode(pInOut);
}
else if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
}
}
BOOL_32 optimized = (tileMode != pIn->tileMode);
if (optimized)
{
*pTileMode = tileMode;
}
return optimized;
HwlOptimizeTileMode(pInOut);
}
/**

25
src/amd/addrlib/core/addrlib1.h
View File

@ -349,15 +349,22 @@ protected:
VOID ComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
/// Pure Virtual function for Hwl checking degrade for base level
virtual BOOL_32 HwlDegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
/// Pure Virtual function for Hwl to get macro tiled alignment info
virtual BOOL_32 HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const = 0;
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
@ -496,8 +503,16 @@ protected:
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
BOOL_32 OptimizeTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, AddrTileMode* pTileMode) const;
VOID OptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
}
static BOOL_32 DegradeTo1D(
UINT_32 width, UINT_32 height,
UINT_32 macroTilePitchAlign, UINT_32 macroTileHeightAlign);
private:
// Disallow the copy constructor

152
src/amd/addrlib/r800/ciaddrlib.cpp
View File

@ -869,6 +869,76 @@ AddrTileMode CiLib::HwlDegradeThickTileMode(
return baseTileMode;
}
/**
****************************************************************************************************
* CiLib::HwlOptimizeTileMode
*
* @brief
* Optimize tile mode on CI
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlOptimizeTileMode(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
// Override 2D/3D macro tile mode to PRT_* tile mode if
// client driver requests this surface is equation compatible
if ((pInOut->flags.needEquation == TRUE) &&
(pInOut->numSamples <= 1) &&
(IsMacroTiled(tileMode) == TRUE) &&
(IsPrtTileMode(tileMode) == FALSE))
{
UINT_32 thickness = Thickness(tileMode);
if (pInOut->maxBaseAlign < Block64K)
{
tileMode = (thickness == 1) ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
}
else if (thickness == 1)
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
}
else
{
static const UINT_32 PrtTileBytes = 0x10000;
// First prt thick tile index in the tile mode table
static const UINT_32 PrtThickTileIndex = 22;
ADDR_TILEINFO tileInfo = {0};
HwlComputeMacroModeIndex(PrtThickTileIndex,
pInOut->flags,
pInOut->bpp,
pInOut->numSamples,
&tileInfo);
UINT_32 macroTileBytes = ((pInOut->bpp) >> 3) * 64 * pInOut->numSamples *
thickness * HwlGetPipes(&tileInfo) *
tileInfo.banks * tileInfo.bankWidth *
tileInfo.bankHeight;
if (macroTileBytes <= PrtTileBytes)
{
tileMode = ADDR_TM_PRT_TILED_THICK;
}
else
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
}
}
}
if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
}
}
/**
****************************************************************************************************
* CiLib::HwlOverrideTileMode
@ -981,48 +1051,6 @@ VOID CiLib::HwlOverrideTileMode(
}
}
// Override 2D/3D macro tile mode to PRT_* tile mode if
// client driver requests this surface is equation compatible
if ((pInOut->flags.needEquation == TRUE) &&
(pInOut->numSamples <= 1) &&
(IsMacroTiled(tileMode) == TRUE) &&
(IsPrtTileMode(tileMode) == FALSE))
{
UINT_32 thickness = Thickness(tileMode);
if (thickness == 1)
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
}
else
{
static const UINT_32 PrtTileBytes = 0x10000;
// First prt thick tile index in the tile mode table
static const UINT_32 PrtThickTileIndex = 22;
ADDR_TILEINFO tileInfo = {0};
HwlComputeMacroModeIndex(PrtThickTileIndex,
pInOut->flags,
pInOut->bpp,
pInOut->numSamples,
&tileInfo);
UINT_32 macroTileBytes = ((pInOut->bpp) >> 3) * 64 * pInOut->numSamples *
thickness * HwlGetPipes(&tileInfo) *
tileInfo.banks * tileInfo.bankWidth *
tileInfo.bankHeight;
if (macroTileBytes <= PrtTileBytes)
{
tileMode = ADDR_TM_PRT_TILED_THICK;
}
else
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
}
}
}
if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
@ -1115,17 +1143,49 @@ VOID CiLib::HwlSelectTileMode(
(pInOut->flags.tcCompatible == FALSE))
{
pInOut->flags.opt4Space = TRUE;
pInOut->maxBaseAlign = Block64K;
// Optimize tile mode if possible
if (OptimizeTileMode(pInOut, &tileMode))
{
pInOut->tileMode = tileMode;
}
OptimizeTileMode(pInOut);
}
HwlOverrideTileMode(pInOut);
}
/**
****************************************************************************************************
* CiLib::HwlSetPrtTileMode
*
* @brief
* Set PRT tile mode.
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlSetPrtTileMode(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
AddrTileType tileType = pInOut->tileType;
if (Thickness(tileMode) > 1)
{
tileMode = ADDR_TM_PRT_TILED_THICK;
tileType = (m_settings.isBonaire == TRUE) ? ADDR_NON_DISPLAYABLE : ADDR_THICK;
}
else
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
tileType = (tileType == ADDR_THICK) ? ADDR_NON_DISPLAYABLE : tileType;
}
pInOut->tileMode = tileMode;
pInOut->tileType = tileType;
}
/**
****************************************************************************************************
* CiLib::HwlSetupTileInfo

5
src/amd/addrlib/r800/ciaddrlib.h
View File

@ -149,8 +149,13 @@ protected:
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;

58
src/amd/addrlib/r800/egbaddrlib.cpp
View File

@ -240,6 +240,18 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoLinear(
&pOut->pitchAlign,
&pOut->heightAlign);
if (pIn->pitchAlign != 0)
{
ADDR_ASSERT((pIn->pitchAlign % pOut->pitchAlign) == 0);
pOut->pitchAlign = pIn->pitchAlign;
}
if (pIn->heightAlign != 0)
{
ADDR_ASSERT((pIn->heightAlign % pOut->heightAlign) == 0);
pOut->heightAlign = pIn->heightAlign;
}
if ((pIn->tileMode == ADDR_TM_LINEAR_GENERAL) && pIn->flags.color && (pIn->height > 1))
{
#if !ALT_TEST
@ -1139,17 +1151,20 @@ AddrTileMode EgBasedLib::ComputeSurfaceMipLevelTileMode(
/**
****************************************************************************************************
* EgBasedLib::HwlDegradeBaseLevel
* EgBasedLib::HwlGetAlignmentInfoMacroTiled
* @brief
* Check if degrade is needed for base level
* Get alignment info for giving tile mode
* @return
* TRUE if degrade is suggested
* TRUE if getting alignment is OK
****************************************************************************************************
*/
BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const
BOOL_32 EgBasedLib::HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] create surface info
UINT_32* pPitchAlign, ///< [out] pitch alignment
UINT_32* pHeightAlign, ///< [out] height alignment
UINT_32* pSizeAlign ///< [out] size alignment
) const
{
BOOL_32 degrade = FALSE;
BOOL_32 valid = TRUE;
ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
@ -1159,6 +1174,7 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
UINT_32 heightAlign;
UINT_32 macroTileWidth;
UINT_32 macroTileHeight;
UINT_32 numSamples = (pIn->numFrags == 0) ? pIn->numSamples : pIn->numFrags;
ADDR_ASSERT(pIn->pTileInfo);
ADDR_TILEINFO tileInfo = *pIn->pTileInfo;
@ -1175,7 +1191,7 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
pIn->bpp,
pIn->width,
pIn->height,
pIn->numSamples,
numSamples,
&tileInfo,
&tileInfo,
pIn->tileType,
@ -1185,7 +1201,7 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
pIn->bpp,
pIn->flags,
pIn->mipLevel,
pIn->numSamples,
numSamples,
&tileInfo,
&baseAlign,
&pitchAlign,
@ -1195,30 +1211,12 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
if (valid)
{
degrade = ((pIn->width < macroTileWidth) || (pIn->height < macroTileHeight));
// Check whether 2D tiling still has too much footprint
if (degrade == FALSE)
{
// Only check width and height as slices are aligned to thickness
UINT_64 unalignedSize = pIn->width * pIn->height;
UINT_32 alignedPitch = PowTwoAlign(pIn->width, pitchAlign);
UINT_32 alignedHeight = PowTwoAlign(pIn->height, heightAlign);
UINT_64 alignedSize = alignedPitch * alignedHeight;
// alignedSize > 1.5 * unalignedSize
if (2 * alignedSize > 3 * unalignedSize)
{
degrade = TRUE;
}
}
}
else
{
degrade = TRUE;
*pPitchAlign = pitchAlign;
*pHeightAlign = heightAlign;
*pSizeAlign = baseAlign;
}
return degrade;
return valid;
}
/**

5
src/amd/addrlib/r800/egbaddrlib.h
View File

@ -137,8 +137,9 @@ protected:
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
virtual BOOL_32 HwlDegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual BOOL_32 HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const;
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo) const;

97
src/amd/addrlib/r800/siaddrlib.cpp
View File

@ -3133,6 +3133,52 @@ UINT_32 SiLib::HwlComputeFmaskBits(
return bpp;
}
/**
****************************************************************************************************
* SiLib::HwlOptimizeTileMode
*
* @brief
* Optimize tile mode on SI
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlOptimizeTileMode(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
if ((pInOut->flags.needEquation == TRUE) &&
(IsMacroTiled(tileMode) == TRUE) &&
(pInOut->numSamples <= 1))
{
UINT_32 thickness = Thickness(tileMode);
pInOut->flags.prt = TRUE;
if (thickness > 1)
{
tileMode = ADDR_TM_1D_TILED_THICK;
}
else if (pInOut->numSlices > 1)
{
tileMode = ADDR_TM_1D_TILED_THIN1;
}
else
{
tileMode = ADDR_TM_2D_TILED_THIN1;
}
}
if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
}
}
/**
****************************************************************************************************
* SiLib::HwlOverrideTileMode
@ -3173,28 +3219,6 @@ VOID SiLib::HwlOverrideTileMode(
break;
}
if ((pInOut->flags.needEquation == TRUE) &&
(IsMacroTiled(tileMode) == TRUE) &&
(pInOut->numSamples <= 1))
{
UINT_32 thickness = Thickness(tileMode);
pInOut->flags.prt = TRUE;
if (thickness > 1)
{
tileMode = ADDR_TM_1D_TILED_THICK;
}
else if (pInOut->numSlices > 1)
{
tileMode = ADDR_TM_1D_TILED_THIN1;
}
else
{
tileMode = ADDR_TM_2D_TILED_THIN1;
}
}
if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
@ -3203,6 +3227,28 @@ VOID SiLib::HwlOverrideTileMode(
}
}
/**
****************************************************************************************************
* SiLib::HwlSetPrtTileMode
*
* @brief
* Set prt tile modes.
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlSetPrtTileMode(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
) const
{
pInOut->tileMode = ADDR_TM_2D_TILED_THIN1;
pInOut->tileType = (pInOut->tileType == ADDR_DEPTH_SAMPLE_ORDER) ?
ADDR_DEPTH_SAMPLE_ORDER : ADDR_NON_DISPLAYABLE;
pInOut->flags.prt = TRUE;
}
/**
****************************************************************************************************
* SiLib::HwlSelectTileMode
@ -3271,10 +3317,7 @@ VOID SiLib::HwlSelectTileMode(
pInOut->flags.opt4Space = TRUE;
// Optimize tile mode if possible
if (OptimizeTileMode(pInOut, &tileMode))
{
pInOut->tileMode = tileMode;
}
OptimizeTileMode(pInOut);
HwlOverrideTileMode(pInOut);
}
@ -3492,8 +3535,6 @@ VOID SiLib::InitEquationTable()
if (m_chipFamily == ADDR_CHIP_FAMILY_SI)
{
static const UINT_32 PrtTileSize = 0x10000;
UINT_32 macroTileSize =
m_blockWidth[equationIndex] * m_blockHeight[equationIndex] *
bpp / 8;

5
src/amd/addrlib/r800/siaddrlib.h
View File

@ -189,8 +189,13 @@ protected:
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual BOOL_32 HwlSanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const
{