Lionel Landwerlin
f86c1b1595
isl: check whether a format is rgb if colorspace is yuv
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Suggested by Chad.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06 11:45:49 +01:00
Lionel Landwerlin
5e9f52ff4d
isl: make format layout channels accessible by index
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06 11:45:44 +01:00
Lionel Landwerlin
c90e50f3a0
vulkan: util: add macros to extract extension/offset number from enums
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v2: Simplify offset enum computation (Jason)
v3: capitalize macros (Chad)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06 11:45:41 +01:00
Samuel Pitoiset
c8ea55ddda
radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flags
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
213f86e514
radv: add RADV_META_SAVE_COMPUTE_PIPELINE flag
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This will allow use to merge the compute save/restore helpers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
ba3dc3519d
radv: add radv_meta_save() helper
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And merge radv_meta_save_novertex() with
radv_meta_save_graphics_reset_vport_scissor_novertex().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
8d91f4e45f
radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASS
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:06 +02:00
Samuel Pitoiset
55ee532932
radv: convert all GFX operations to the RADV_META_SAVE_XXX flags
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
807f2d4f33
radv: introduce the concept of meta save flags
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This will allow us to save/restore the different states on-demand
based on the meta operation. For now, this saves/restores all
states. Compute will follow once the graphics part is done.
The main idea is to merge all save/restore helpers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
a3a497c921
radv: remove unused RADV_META_VERTEX_BINDING_COUNT
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
b269ed3d94
radv: select the pipeline outside of the loop when decompressing htile
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Samuel Pitoiset
507df35939
radv: add radv_htile_enabled() helper
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-06 09:49:05 +02:00
Tapani Pälli
0351638284
i965: pass wanted format to intel_miptree_create_for_dri_image
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Change b3a44ae7a4
caused regressions on Android where DRI and renderbuffer
can disagree on the format being used. This patch removes the colorspace
parameter and instead we pass renderbuffer format. For non-winsys images we
still do srgb/linear modification in same manner as change b3a44ae7a4
wanted
but take format from renderbuffer instead of DRI image.
This patch fixes regressions seen with following test sets:
dEQP-EGL.functional.color_clears*
dEQP-EGL.functional.render*
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102999
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06 08:06:13 +03:00
Marek Olšák
c4d1a199f8
radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival Evolved
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v2: use DB_META | PS_PARTIAL_FLUSH
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
2017-10-06 02:56:11 +02:00
Marek Olšák
15d918e46f
radeonsi: inline struct si_sampler_views
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
23cdde5138
radeonsi: rename si_textures_info -> si_samplers, si_images_info -> si_images
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
3dfb375446
radeonsi: fold needs_*_decompress_mask update into si_set_sampler_view
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
bd5509d0a8
radeonsi: simplify a loop in si_update_fb_dirtiness_after_rendering
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
bcd3e761a3
ac: properly document a buffer.store LLVM workaround
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
cceb916456
radeonsi: use f32_0 and f32_1
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
1516059ab1
radeonsi: fold *gallivm
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
e1b83c67da
radeonsi: lp_type::length is always 1
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
906ee3a3ba
radeonsi: don't use bld.elem_type
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
723a23905f
radeonsi: don't use lp_build_const_*
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
b4600b4740
radeonsi: use ctx->ac.context and ctx->types
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
d0751f6c1f
radeonsi: use ctx->ac.builder
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
82dc72c8bd
radeonsi: use ctx->i/f32 types more
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
dcbd3d470c
radeonsi: use i32_0 and i32_1 more
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
bacdf5a928
radeonsi: use bitcast in a few places
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
ad7305aa96
radeonsi: use ac helpers for bitcasts
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
9a88580a4b
glsl_to_tgsi: skip UARL for 1D registers if the driver doesn't need it
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
1bf1bfc12a
glsl_to_tgsi: handle reladdr as TEMP in rename_temp_registers and dead_code
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
8602c6a326
glsl_to_tgsi: each reladdr object should have only one parent
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required by rename_temp_registers.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
985338e2cb
glsl_to_tgsi: fix instruction order for bindless textures
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We emitted instructions loading the bindless handle after the memory
instruction.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
bd1837471a
glsl_to_tgsi: enable copy propagation for tessellation shaders
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just don't propagate output reads
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
dbe16d7537
radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
44993bd26f
radeonsi: use si_get_indirect_index for TEMP indexing
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
e986a16c16
radeonsi: use si_get_indirect_index for CONST indexing
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
212c612a63
tgsi/ureg: allow any register file in address operands
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Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
41b85158ab
gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
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Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
cb686a340f
tgsi/scan: scan address operands (v2)
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v2: set swizzled usage mask
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
37714c6df2
tgsi/scan: set correct usage mask for tex offsets in scan_src_operand
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
5cc779197c
tgsi/scan: take advantage of already swizzled usage mask in scan_src_operand
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It has always been a usage mask *after* swizzling.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
ea85b76519
tgsi/scan: set non-valid src_index for tex offsets in scan_src_operand
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tex offsets are not "Src" operands.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
be3ab867bd
tgsi: implement tgsi_util_get_inst_usage_mask properly
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All opcodes are handled.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Marek Olšák
bb8abc10bf
tgsi: add docs for some existing pack opcodes
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-06 02:56:11 +02:00
Bas Nieuwenhuizen
4ffb9890ef
radv: Enable VK_KHR_maintenance2 extension.
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Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00
Bas Nieuwenhuizen
0c90ca7d37
radv: Make tess winding order a bit more intuitive.
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Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00
Bas Nieuwenhuizen
c62afd094d
radv: Allow setting the domain origin in tess.
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Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00
Bas Nieuwenhuizen
ca21634632
radv: Disable usage checks in metadata for images with extended usage data.
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The app can extend the usage, so knowing that the usage is limitied
does not help us here.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-06 01:41:29 +02:00