Commit Graph

75015 Commits

Author SHA1 Message Date
Eric Anholt f61ceeb3fd vc4: Enable MSAA.
We still have several failures in the newly enabled tests in simulation:
sRGB downsampling is done as if it was just linear, stencil blits are not
supported on MSAA either, and derivatives are still not supported
(breaking some MSAA simulation shaders).  So, other than sRGB downsampling
quality, things seem to be in good shape.
2015-12-08 10:09:52 -08:00
Eric Anholt fc4a1bfb88 vc4: Add support for mapping of MSAA resources.
The pipe_transfer_map API requires that we do an implicit
downsample/upsample and return a mapping of that.
2015-12-08 09:49:56 -08:00
Eric Anholt 6b4dfd53ae vc4: Add support for texel fetches from MSAA resources.
This is the core of ARB_texture_multisample.  Most of the piglit tests for
GL_ARB_texture_multisample require GL 3.0, but exposing support for this
lets us use the gallium blitter for multisample resolves.  We can
sometimes multisample resolve using just the RCL, but that requires that
the blit is 1:1, unflipped, and aligned to tile boundaries.
2015-12-08 09:49:55 -08:00
Eric Anholt a97b40dca4 vc4: Add support for multisample framebuffer operations.
This includes GL_SAMPLE_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, and
GL_SAMPLE_ALPHA_TO_COVAGE.

I haven't implemented a dithering function yet, and gallium doesn't give
me a good chance to do so for GL_SAMPLE_COVERAGE.
2015-12-08 09:49:54 -08:00
Eric Anholt edc3305de7 vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.
I only stumbled on this while experimenting due to reading about HW-2905.
I don't know if the EZ disable in the Z-clear is actually necessary, but
go with it for now.
2015-12-08 09:49:54 -08:00
Eric Anholt edfd4d853a vc4: Add support for drawing in MSAA. 2015-12-08 09:49:53 -08:00
Eric Anholt e7c8ad0a6c vc4: Add kernel RCL support for MSAA rendering. 2015-12-08 09:49:53 -08:00
Eric Anholt 568d3a8e32 vc4: Rename color_ms_write to color_write.
I was thinking this was the only MSAA resolve thing, so it should be noted
separately, but actually load/store general also do MSAA resolve.
2015-12-08 09:49:52 -08:00
Eric Anholt bf92017ace vc4: Allow RCL blits to the edge of the surface.
The recent unaligned fix successfully prevented RCL blits that weren't
aligned inside of the surface, but we also want to be able to do RCL blits
for the whole surface when the width or height of the surface aren't
aligned (we don't care what renders inside of the padding).
2015-12-08 09:49:52 -08:00
Eric Anholt fb4877dbab vc4: Add disabled debug printf for describing blits.
I keep typing variants of this while debugging RCL blits for MSAA.
2015-12-08 09:49:51 -08:00
Eric Anholt 2792d118f1 vc4: Fix check for tile RCL blits with mismatched y.
This was a typo in 3a508a0d94 that didn't
show up in testcases at that moment.
2015-12-08 09:49:51 -08:00
Eric Anholt 1529f138ff vc4: Fix compiler warning from size_t change.
I missed this when bringing over the kernel changes.
2015-12-08 09:49:50 -08:00
Olivier Pena a5256012ef scons: support for LLVM 3.7.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-08 13:53:31 +00:00
Dave Airlie bd47fcd57b docs/GL3.txt: consolidate r600 GL4.1.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-08 20:13:14 +10:00
Jason Ekstrand 18069dce4a i965: Make uniform offsets be in terms of bytes
This commit pushes makes uniform offsets be terms of bytes starting with
nir_lower_io.  They get converted to be in terms of vec4s or floats when we
cram them in the UNIFORM register file but reladdr remains in terms of
bytes all the way down to the point where we lower it to a pull constant
load.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand 813f0eda8e i965/nir_uniforms: Replace comps_per_unit with an is_scalar boolean
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand 22c273de2b i965/nir: Remove unused indirect handling
The one and only place where the FS backend allows reladdr is on uniforms.
For locals, inputs, and outputs, we lower it away before the backend ever
sees it.  This commit gets rid of the dead indirect handling code.

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand abb569ca18 i965/state: Get rid of dword_pitch arguments to buffer functions
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand 05bdc21f84 i965/vec4: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand 13ad8d03f2 i965/fs: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Jason Ekstrand e3e70698c3 i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on
vec4-aligned byte offsets on Iron Lake and below and worked in terms of
vec4 offsets on Sandy Bridge.  On Ivy Bridge, we add a new *LOAD_GEN7
variant which works in terms of vec4s.  We're about to change the GEN7
version to work in terms of bytes, so this is a nice unification.

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:51:23 -08:00
Ben Widawsky 6ef8149bcd i965: Fix texture views of 2d array surfaces
It is legal to have a texture view of a single layer from a 2D array texture;
you can sample from it, or render to it. Intel hardware needs to be made aware
when it is using a 2d array surface in the surface state. The texture view is
just a 2d surface with the backing miptree actually being a 2d array surface.
This caused the previous code would not set the right bit in the surface state
since it wasn't considered an array texture.

I spotted this early on in debug but brushed it off because it is clearly not
needed on other platforms (since they all pass). I have no idea how this works
properly on other platforms (I think gen7 introduced the bit in the state, but I
am too lazy to check). As such, I have opted not to modify gen7, though I
believe the current code is wrong there as well.

Thanks to Chris for helping me debug this.

v2: Just use the underlying mt's target type to make the array determination.
This replaces a bug in the first patch which was incorrectly relying only
on non-zero depth (not sure how that had no failures). (Ilia)

Cc: Chris Forbes <chrisf@ijw.co.nz>
Reported-by: Mark Janes <mark.a.janes@intel.com> (Jenkins)
References: https://www.opengl.org/registry/specs/ARB/texture_view.txt
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-12-07 18:47:04 -08:00
Nicolai Hähnle d5a5dbd71f radeonsi: last_gfx_fence is a winsys fence
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-07 21:15:59 -05:00
Ilia Mirkin f97f755192 nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integers
For some reason this has been disabled for integers ever since codegen
was merged, despite there being emission code for IMAD. Seems to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-07 18:49:28 -05:00
Ilia Mirkin 1d708aacb7 gk110/ir: fix imad sat/hi flag emission for immediate args
According to nvdisasm both the immediate and non-imm cases use the same
bits. Both of these flags are quite rarely set though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 18:49:28 -05:00
Kenneth Graunke 87a1166310 i965: Add brw_device_info::min_ds_entries field.
From the 3DSTATE_URB_DS documentation:

"Project: IVB, HSW
 If Domain Shader Thread Dispatch is Enabled then the minimum number of
 handles that must be allocated is 10 URB entries."

"Project: BDW+
 If Domain Shader Thread Dispatch is Enabled then the minimum number of
 handles that must be allocated is 34 URB entries."

When the HS is run in SINGLE_PATCH mode (the only mode we support
today), there is no minimum for HS - it's just zero.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes 42ca675cc9 i965: Add state bits for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes 80ea18d1a1 i965: Add backend structures for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:55 -08:00
Chris Forbes 5340f37902 i965: Set core tessellation-related limits
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Kenneth Graunke a9e6a56a02 i965: Request lowering of gl_TessLevel* from float[] to vec4s.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Kenneth Graunke 7a17356800 i965: Create new files for HS/DS/TE state upload code.
For now, this just splits the existing code to disable these stages into
separate atoms/files.  We can then replace it with real code.

v2: Bump the render atoms in this patch so it compiles (in my branch,
    I'd bumped it in an earlier patch).  61 seems to be the minimum
    that works, which doesn't match the old value + the number of atoms
    I added in this patch, so apparently we had some slop before.

v3: Actually disable the DS unit on Gen8+.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-12-07 14:48:54 -08:00
Ilia Mirkin 63b850403c gk104/ir: sampler doesn't matter for txf
We actually leave the sampler unset for OP_TXF, which caused the GK104+
logic to treat some texel fetches as indirect. While this works, it's
incredibly wasteful. This only happened when the texture was > 0 (since
sampler remained == 0).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 16:22:54 -05:00
Marek Olšák 32f05fadbb radeonsi: disable DCC on Stoney
Cc: 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-07 22:01:08 +01:00
Sonny Jiang 2618886600 winsys/amdgpu: addrlib - port a Fiji bug fix
Fiji: Fixed tiled resource failures

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

v2: fix a compile failure (typo) - Marek
2015-12-07 21:58:42 +01:00
Sonny Jiang 338d7bf053 winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-07 21:58:42 +01:00
Sonny Jiang 676bc25140 winsys/amdgpu: addrlib - port fix error for workaround for 1D tiling
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-07 21:58:42 +01:00
Christian König a2c5200a4b st/va: disable MPEG4 by default v2
The workarounds are too hacky to enable them by default
and otherwise MPEG4 doesn't work reliably.

v2: add docs/envvars.html, CC stable and fix typos

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v1)
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Cc: "11.1.0" <mesa-stable@lists.freedesktop.org>
2015-12-07 20:34:17 +01:00
Christian König ca3e2b76c0 st/va: move HEVC functions into separate file v2
v2: actually copy all of it

Signed-off-by: Christian König <christian.koenig@amd.com>
2015-12-07 20:34:17 +01:00
Alejandro Piñeiro 3d260cc653 mesa: remove _mesa_tex_target_is_array
_mesa_is_array_texture provides the same functionality and:

1. it returns bool instead of GLboolean
2. it's not related to the texture format (texformat.c)
3. the name's a little shorter

v2: remove _mesa_tex_target_is_array instead (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-07 20:31:20 +01:00
Alejandro Piñeiro b16e0ff34e i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_array
Both methods provide the same functionality, so one would be
removed.

v2: use _mesa_is_array_texture and not the other way (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-07 20:30:24 +01:00
Ilia Mirkin db072d2086 gk110/ir: fix imul hi emission with limm arg
The elemental demo hits this case.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-07 13:30:17 -05:00
Brian Paul 32a6e081c3 svga: use the debug callback to report issues to the state tracker
Use the new debug callback hook to report conformance, performance
and fallbacks to the state tracker.  The state tracker, in turn can
report this issues to the user via the GL_ARB_debug_output extension.

More issues can be reported in the future; this is just a start.

v2: remove conditionals around pipe_debug_message() calls since the
check is now done in the macro itself.
v3: remove unneeded dummy %s substitutions

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>,
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-12-07 08:57:49 -07:00
Brian Paul 5effc3ae74 gallium/util: check callback pointers for non-null in pipe_debug_message()
So the callers don't have to do it.

v2: also check cb!=NULL in the macro

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-12-07 08:56:51 -07:00
Abdiel Janulgue b19546abf3 i965: Add defines for gather push constants
v2 (Francisco Jerez):
   - Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
   - Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANT_*.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2015-12-07 14:58:12 +02:00
Timothy Arceri 9214664aed mesa: move GLES checks for SSO input/output validation
This function is unfinished there is a bunch more validation rules
that need to be applied here. We will still want to call it for desktop
GL we just don't want to validate precision so move the ES check to
reflect this.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-07 21:41:14 +11:00
Timothy Arceri ad02621854 mesa: move GL_INVALID_OPERATION error to rendering call
The validation api doesn't trigger this error so just move it to the
code called during rendering.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:41:09 +11:00
Timothy Arceri 4dd096d741 mesa: move pipeline input/output validation inside _mesa_validate_program_pipeline()
This allows validation to be done on rendering calls also.

Fixes 3 dEQP-GLES31.functional.separate tests.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
2015-12-07 21:41:05 +11:00
Timothy Arceri da1a01361b glsl: re-validate program pipeline after sampler change
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=93180
2015-12-07 21:41:00 +11:00
Dave Airlie 41e82f4f96 r600: apply SIMD workaround to cayman also.
At last on ARUBA this is required to stop tessellation hanging
in heaven.

This removes one of the SIMDs from use by the HS/LS.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 18:57:34 +10:00
Dave Airlie 6bf6bdbc2b r600: fix regression introduced with ring emit changes.
This was adding one after a CUT which broke end primitive
2015-12-07 05:44:55 +00:00