Commit Graph

155928 Commits

Author SHA1 Message Date
Ella Stanforth f392b6c1ad v3dv: Implement VK_KHR_performance_query
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14061>
2022-06-27 07:34:16 +00:00
Erico Nunes f2a24fd4a2 ci: Revert "CI: Lima farm is offline"
The lab is up and running again.

This reverts commit 686e20afcd.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17240>
2022-06-27 07:02:30 +00:00
Qiang Yu 04b15f88e7 radeonsi: replace llvm gs input handle with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:50 +08:00
Qiang Yu 36197b8dc0 ac/llvm: get back nir_intrinsic_load_gs_vertex_offset_amd
Will be used by radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:46 +08:00
Qiang Yu e9f1f115fa ac/nir: add triangle_strip_adjacency_fix to gs input lower
From radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:43 +08:00
Qiang Yu f8ddee90ca radeonsi: replace llvm es output with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:38 +08:00
Qiang Yu 109eb378e5 ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it
directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:34 +08:00
Qiang Yu 8b5e8b2af7 ac/nir: remove unused param num_reserved_es_outputs from gs input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:30 +08:00
Qiang Yu c66eba2072 radeonsi: set lds for gs/es to handle nir shared memory load/store
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:26 +08:00
Qiang Yu 7ddd15f6c7 ac/nir: skip gl_ViewportIndex and gl_Layer write in ES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:21 +08:00
Qiang Yu 06d493dde2 radeonsi: implement two esgs ring nir intrinsic
nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd

Will be used by esgs lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:15 +08:00
Qiang Yu 9fc01f6e79 ac/llvm: fix code format alignment in visit_load_local_invocation_index
Used tab instead of space.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:00 +08:00
Qiang Yu 7847114343 radeonsi: replace llvm tes input load with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 6b6aeeecbb radeonsi: set uses_vmem_load_other for nir_intrinsic_load_buffer_amd
Before lower TES load input to load buffer, mark this flag for this
intrinsic, otherwise we get corruption with GFX10 after the lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2b7e167bbd radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 7598bfd768 radeonsi: replace llvm tcs output with nir lower pass
Remove the store_tcs_outputs abi, we can use common output abi
to handle the tessfactor pass as vgpr.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu d00845faf4 ac/nir: add no_input_lds_space param to hs output lower
This is used by radeonsi to save some lds space when all LS output
is passed by register.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 8f8d06bd05 ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd
tess lowering may generate buffer store with partial write mask.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu baaeca7d1a radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes
radv will lower this intrinsic before gets to llvm, so we just need to
implement it in radeonsi.

The tes version will be used in tess lower too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3853dfcd44 radeonsi: implement nir_intrinsic_load_ring_tess_offchip(_offset)_amd
Used by tess lower latter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 4ec864c057 radeonsi: preload tess offchip ring for tcs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu ae9b02b4d0 ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem
Used by radeonsi and radv to reflect true wave size used, not minimal size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 18d51831a8 ac/nir: add pass_tessfactors_by_reg param to hs output lower
radeonsi won't emit tess factor in the lower pass, need to keep
the output for llvm backend to pass it as parameter. This is used
by radeonsi for an optimization to save LDS write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 6ccb9634de ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower
radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu fdf589321c ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd
Also add radv and radeonsi implementation. Will be used in tess lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2ba6d2b107 ac/nir: remove unused parameter in tes input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 07e025a390 radeonsi: implement nir_intrinsic_load_tcs_num_patches_amd
Used by ac_nir_lower_tess_io_to_mem.c.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu a1763ad4b3 radeonsi: replace llvm based fixed tcs with nir
Create nir passthrough shader with explicit input/output and vertex
output count so that it can be handled by compiler same as user tcs.

The drawback is we create more si_shader_selector with different
input/output and vertex output count which was handled by compiler
backend before.

As fixed function tcs can be handled like user tcs, we don't need
the dedicated fixed_func_tcs_shader state either.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3ab9c42b43 radeonsi: add si_create_passthrough_tcs
For replacing si_create_fixed_func_tcs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 74350cf057 radeonsi: support multi stage shader state creation in nir shaderlib
For creating tcs passthrough shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu a599576654 radeonsi: use si_shader as parameter in si_get_nir_shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 05b829cd0c radeonsi: deserialize nir binary in si_check_blend_dst_sampler_noop
We can do this parse with original nir instead of shader key pass
applied nir in si_get_nir_shader.

This can free si_get_nir_shader to just use si_shader as parameter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3aa70d92ce radv: no need to do gs_alloc_req for newer chips in ngg vs/tes
Copy from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Qiang Yu 74e596a5f0 ac/llvm: conditionally check wave id in gs sendmsg
nir lowering already call this with wave id check, no need to
check inside ac_build_sendmsg_gs_alloc_req again.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Bas Nieuwenhuizen e75f11625d radv: Deal with derefs from opaque types in function parameters.
Needs more copy propagation before nir_opt_derefs picks it up.

Note that the full general problem of opaque types stored in
intermediate variables is still open, but that seems like a whole
can of worms, and no sense to have gfxbench stay broken during the
time it takes to solve that.

Cc: mesa-stable
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5945
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17012>
2022-06-27 01:23:43 +00:00
Alessandro Astone a7d6365f20 Android.mk: Intermediate output paths may already be absolute
That is the case when OUT_DIR_COMMON_BASE is set.
Only prefix paths with AOSP_ABSOLUTE_PATH if they're relative.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
2022-06-26 22:06:36 +00:00
Alessandro Astone 5feb025086 Android.mk: Generate the dummy source in local-generated-sources-dir
A source file cannot be otherwise referenced by absolute path.
That happens when OUT_DIR_COMMON_BASE is set.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
2022-06-26 22:06:36 +00:00
Alessandro Astone b0a1a28d97 Android.mk: Make mesa3d-lib work with absolute path meson outputs
LOCAL_PREBUILT_MODULE_FILE is the only variable that allows
specifying the absolute path to a prebuilt.
That happens when OUT_DIR_COMMON_BASE is set.

Since it does not have multilib variants, define two separate
libraries for multilib

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
2022-06-26 22:06:36 +00:00
Alessandro Astone 46d4a0f8b2 Android.mk: Cleanup mesa3d-lib
Properly cleanup variables before declaring a library.
Explicitly require library dependencies.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
2022-06-26 22:06:36 +00:00
Kenneth Graunke b28efd80eb iris: Update comment about 2GB dynamic state range
We tracked this down with the HW teams back in 2020 and there's now a
documented workaround.  Comments from the HW team say this applies all
the way through XeHP but we're not sure beyond that.

This is a bug that we hit but the Windows drivers didn't because Jason
decided to allocate our memory structures from the top end of the VMA
range explicitly to catch bugs like this, while Windows allocates from
zero and up, so they would need to allocate more than 2GB of dynamic
state before running into it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4880
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17216>
2022-06-24 23:30:12 +00:00
Ryan Neph 627ba5c91b venus: support VK_KHR_copy_commands2
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17226>
2022-06-24 23:20:05 +00:00
Ryan Neph 8b81098519 venus: enable VK_EXT_image_view_min_lod
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17227>
2022-06-24 23:09:48 +00:00
Ryan Neph f862cc070f venus: update venus-protocol with VK_EXT_image_view_min_lod
Copy in auto-generated protocol bindings.

Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17227>
2022-06-24 23:09:48 +00:00
Jason Ekstrand 21374eb777 vulkan/render_pass: Support VkAttachmentSampleCountInfoAMD
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Jason Ekstrand 541819b2d6 vulkan/render_pass: Allow for mixed sample counts
RADV supports VK_AMD_mixed_attachment_samples which does exactly what it
sounds like.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Jason Ekstrand 7e11cdc77a vulkan/render_pass: Pass sample locations to barriers
This is required for depth/stencil images created with
VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Jason Ekstrand 6216c59dbb vulkan/render_pass: Use a special layout for self-dependencies
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Jason Ekstrand f10012a2b2 anv: Use CmdBeginRendering for resumes in BeginCommandBuffer when possible
This lets us avoid the code duplication between BeginRendering and
BeginCommandBuffer and also lets us stop crawling core render pass
structs directly and instead focus on dynamic rendering concepts.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Jason Ekstrand 3a204d5cf3 vulkan/render_pass: Add a better helper for render pass inheritance
Instead of making drivers dive into the render pass and framebuffer
themselves, provide a helper that constructs a VkRenderingInfo for a
render pass resume that they can use instead.  This should reduce code
duplication between driver implementations of BeginRendering and
BeginCommandBuffer.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
2022-06-24 22:37:53 +00:00
Mike Blumenkrantz f904b95ef0 zink: add a turnip driver workaround for EXT_depth_clip_enable
this is broken

ref #6732

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17237>
2022-06-24 19:54:44 +00:00