Commit Graph

113987 Commits

Author SHA1 Message Date
Alyssa Rosenzweig ac6aa93f9e panfrost: Unify ctx->vs and ctx->fs
It's a little verbose, but this way we can support other shader stages
without too much contortion.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:03 -07:00
Alyssa Rosenzweig 4b93152c29 panfrost: Flesh out launch_grid stub
It's still incomplette, but we're able to hook into launch_grid to
create a stub COMPUTE job.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:02 -07:00
Alyssa Rosenzweig cd1be4605c panfrost: Cleanup via payload unification
Since these are now indexable, quite a bit of code cleans up.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:02 -07:00
Alyssa Rosenzweig 0da52015a1 panfrost: Unify payload_vertex/payload_tiler
Rather than disparate variables, let's use an array of payloads indexed
by the shader stage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:02 -07:00
Alyssa Rosenzweig 902115f94f panfrost: Only wallpaper if we drew something
last_tiler.gpu may be NULL at flush time despite no clear and existing
jobs -- if we executed a compute-only workload.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:02 -07:00
Alyssa Rosenzweig 2d86828243 panfrost: Adjust shader CAPs to expose dEQP compute
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig 39fe9f5e2f panfrost: Expose NIR as our PIPE_SHADER_CAP_SUPPORTED_IRS
We *could* expose TGSI as well -- we pipe it through tgsi_to_nir for
Gallium-internal shaders anyway -- but we'd rather not.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig 1697760e05 panfrost: Copy freedreno's panfrost_get_compute_param
Values reported here aren't remotely correct, but it's a start to just
get the entrypoint stubbed out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig c8bc664447 panfrost: Expose COMPUTE-related caps for GLES3.1
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig 5a8b83ca0b panfrost: Stub out launch_grid
Just dumps some information about the invocation for later debug.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig a8fc40aaf5 panfrost: Stub out compute CSO
Doesn't do anything, just gets the functions there.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:23:01 -07:00
Alyssa Rosenzweig e913986868 panfrost: Implement gl_FrontFacing
Interestingly, this requires no compiler changes. It's just exposed as a
special varying.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:15:03 -07:00
Alyssa Rosenzweig f3e15122d4 panfrost: Add support for decoding gl_FrontFacing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:15:03 -07:00
Alyssa Rosenzweig 9e66ff3ea9 pan/decode: Use max varying index as varying buffer count
This allows us to decode asymmetric varyings correctly, which occurs
with e.g. gl_FrontFacing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-01 16:15:03 -07:00
Timothy Arceri 2afedfaf9a iris: add support for gl_ClipVertex in tess eval shaders
Required for OpenGL compat support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-01 16:12:37 -07:00
Timothy Arceri 00b5bf2d72 iris: add support for gl_ClipVertex in geometry shaders
This will enable us to support the OpenGL compat profile.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-01 16:12:27 -07:00
Jason Ekstrand 70dc017aec nir: Stop whacking gl_FrontFacing to a system value
We have a cap bit for gallium and a GLSL compiler flag to control this.
Just trust what GLSL gives us and stop forcing it.  In order for this to
be safe, we have to advertise another cap in some of the gallium
drivers.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-01 21:59:37 +00:00
Alyssa Rosenzweig 4e736b88f3 panfrost: Implement panfrost_set_shader_buffers callback
Just copy over the passed SSBO for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-01 14:32:08 -07:00
Alyssa Rosenzweig 898a18ea89 gallium/util: Add util_set_shader_buffers_mask helper
Conceptually follows util_set_vertex_buffers_mask but for SSBOs.

v2: Fix missing ~ when clearing mask. Adjust mask behaviour to match
freedreno/v3d when buffer == NULL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-01 14:31:56 -07:00
Jonathan Marek 3e33173200 kmsro: move entry points from etnaviv to kmsro
These drivers are kmsro drivers so they should be part of the kmsro #if

This fixes missing imx_drm driver when building with only freedreno+kmsro

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-01 16:31:51 -04:00
Emil Velikov 85dace1c0b gitlab-ci: remove software-properties-common
Currently we use the python package to manage repositories. At the same
time we also do that by hand - since it's a trivial echo to a file.

Stay consistent, remove the package and manage things manually.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-08-01 16:16:15 +00:00
Brian Paul 3307c85a7d st/mesa: fix MSVC compile breakage
Trivial.
2019-08-01 09:07:21 -06:00
Gert Wollny 9de00e74fe virgl: Enable depth_clamp by lowering if the host is new enough.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny b2e92c45ce gallium: Make PIPE_CAP_DEPTH_CLIP_DISABLE a tri-state value and use it
Use value "2" to signal that lowering is needed and supported and enable
it accordingly.

v2: - Note in CAP description that this lowering currently requires TGSI
    - use "true" instead of GL_TRUE (both Erik)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny 616f320745 mesa/st: Signal state changes when depth_clamp is emulated
v1 implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: - Add GS and TES
    - fix constants state update flags (Erik)
v3: don't update rasterizer when depth_clamp is lowered (Erik)
v4: Correct NewDepthClamp and also set flags for NewClipControl (Erik)
v5: Also set shader_has_one_variant property acording to possible
   depth_clamp lowering (Marek)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny d004fcc04a mesa/st: Add depth clamping to rasterizer code
implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>

v2: Use current depth range values for clamping (Erik)
v3: fix scons-win64 build

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny 57361d89fa mesa/st: Tie depth_clamp code into other shaders (GS and TES)
v2: Use file scope defined depth_range_state  in common
v3: - don't use the one_shader_variant property, as this is
      not correct (Marek)
    - also use tests on available shader stages to enable
      depth_clamp lowering
v4: Don't use key.st, use st directly (Marek)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny d81ba38b02 mesa/st: Tie depth_clamp lowering into the FS
v1 implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: Use different call for FS
v3: Use file scope defined depth_range_state

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny fefb152067 mesa/st: Tie depth clamp lowering in to the VP code
v1: implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: Add handling of the ARB_clip_control depth mode
v3: Move depth_range_state to file scope and remove training zeros (Erik)
v4: - don't use the one_shader_variant property, as this is not correct (Marek)
    - also use tests on available shader stages to enable depth_clamp lowering
V5: Don't use key.st, use st directly (Marek)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Erik Faye-Lund b048d8bf8f mesa/st: add tgsi-lowering code for depth-clamp
This is a TGSI pass that lowers depth-clamping into shader-operations,
by replacing the depth-value with 0 (a z-coordinate of zero will always
pass the OpenGL depth test conditions), and using a dedicated varying to
interpolate the real depth-value instead. Finally we replace the
depth-output in the fragment shader.

v1 implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: Add support for handling depth clip mode, and refactor code
v3: - Rename *_vs functions to *_last_vertex_stage (Erik)
    - Use 0.0 depth to avoid clipping (Erik)
v4: Fix inversion of bool value for clip control property

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny 78ba12f40f mesa/st: replace boolean declarations by bool
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-01 05:58:53 +00:00
Gert Wollny 7fb47195d8 Revert "softpipe: Don't draw when rasterizer_discard is set"
This was too aggressive and breaks TF (Ilia)

This reverts commit 4ee638cd78.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-08-01 05:57:41 +00:00
Eric Engestrom a563bb9e28 docs: reword meson instructions
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-08-01 00:42:02 +01:00
Eric Engestrom 8a1e803643 travis: drop unnecessary Meson option for MacOS
Those are already their default values on MacOS.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-01 00:25:20 +01:00
Jason Ekstrand b539157504 intel/vec4: Drop all of the 64-bit varying code
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-31 18:14:09 -05:00
Jason Ekstrand d03ec807a4 intel/fs: Drop all of the 64-bit varying code
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-31 18:14:09 -05:00
Jason Ekstrand 942c759059 intel: Use NIR to lower 64-bit varying access
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-31 18:14:09 -05:00
Jason Ekstrand 078dcb7ccd nir/lower_io: Add an option to lower 64-bit varyings
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-31 18:14:09 -05:00
Jorge Natz a63e82deb5 docs: Update Platforms and Drivers page with more comprehensive information.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-31 22:50:43 +00:00
Dave Airlie 7ad6ec80d9 nir: use common deref has indirect code in scratch lowering.
This doesn't seem to need it's own copy here.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-01 08:32:12 +10:00
Eric Engestrom 5d7bcac4e7 nir: remove explicit nir_intrinsic_index_flag values
These were left after a rebase and happen to make
NIR_INTRINSIC_SWIZZLE_MASK == NIR_INTRINSIC_SRC_ACCESS, which is how it
was noticed.

Fixes: 6f20643b47 ("nir: Allow qualifiers on copy_deref and image instructions")
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-31 23:28:20 +01:00
Yevhenii Kolesnikov 830a8e6c47 state_tracker: Free Labels for querry and tranform_feedback
Memory leaks were observed on iris with GL_KHR_debug.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-31 22:16:42 +00:00
Kenneth Graunke b61f17d362 iris: Skip emitting 3DSTATE_INDEX_BUFFER if possible
We were emitting 3DSTATE_INDEX_BUFFER on every indexed draw, even if
back-to-back draws referred to the same index buffer.  This improves
drawoverhead scores in the DrawElements cases by about 10%, by giving
us even more minimal batches.
2019-07-31 15:14:10 -07:00
Mike Blumenkrantz 8af1990ad7 st/dri: simplify dri_get_egl_image by reusing dri2_format_table
this makes dri2_get_mapping_by_fourcc accessible from dri_helpers.h
and does a direct lookup on the fourcc id to match the pipe format

v2 (Ken): Allow map to be NULL, use img->texture->format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-31 15:11:15 -07:00
Erico Nunes 82bf5a8aac lima: enable lower_bitops in ppir
The mali pp doesn't support integers and some nir_algebraic
optimizations may result in ops that are not easily lowerable to floats,
so disable optimizations resulting in bitops.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-07-31 23:06:26 +02:00
Erico Nunes b3676a6548 nir/algebraic: rename lower_bitshift to lower_bitops
Optimizations that insert bitshift or bitwise operations should not be
applied on GPUs that don't support integer operations.
The .lower_bitshift could be used to control the bitshift related ones,
but there was also one bitwise optimization uncovered.
Since only lima and freedreno use this option and the use case is that
no bit operations are wanted, let's rename it to .lower_bitops and use
it to control all bitops related optimizations.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-07-31 23:06:04 +02:00
Erico Nunes 99c956fb47 lima/ppir: lower fdot in nir_opt_algebraic
Now that we have fsum in nir, we can move fdot lowering there.
This helps reduce ppir complexity and enables the lowered ops to be part
of other nir optimizations in the optimization loop.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-31 21:35:58 +02:00
Erico Nunes 4a407df682 nir/algebraic: add new fsum ops and fdot lowering
The Mali400 pp doesn't implement fdot but has fsum3 and fsum4, which can
be used to optimize fdot lowering. fsum2 is not implemented and can be
further lowered to an add with the vector components.
Currently lima ppir handles this lowering internally, however this
happens in a very late stage and requires a big chunk of code compared
to a nir_opt_algebraic lowering.
By having fsum in nir, we can reduce ppir complexity and enable the
lowered ops to be part of other nir optimizations in the optimization
loop.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-31 21:35:58 +02:00
Erico Nunes 7f8ff686b7 lima/ppir: refactor texture code to simplify scheduler
The 'varying fetch' pp instruction deals only with coordinates, and
'texture fetch' deals only with the sampler index.
Previously it was not possible to clearly map ppir_op_load_coords and
ppir_op_load_texture to pp instructions as the source coordinates were
kept in the ppir_op_load_texture node, making this harder to maintain.
The refactor is made with the attempt to clearly map ppir_op_load_coords
to the 'varying fetch' and ppir_op_load_texture to the 'texture fetch'.
The coordinates are still temporarily kept in the ppir_op_load_texture
node as nir has both sampler and coordinates in a single instruction and
it is only possible to output one ppir node during emit. But now after
lowering, the sources are transferred to the (always) created
ppir_op_load_coords node, and it should be possible to directly map them
to their pp instructions from there onwards.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-31 21:22:41 +02:00
Erico Nunes d2901de09e lima/ppir: lower texture projection
Lower texture projection in ppir using nir_lower_tex and nir_lower_tex.
This will insert a mul with the coordinate division before the load
varying.

Even though the lima pp supports projection in the load varying
instruction while loading the coordinates (from a register or a
varying), it requires that both the coordinates and projector be
components in a single register.
nir currently handles them in separate ssa, and attempting to merge them
manually may end up in worse code than just doing the coordinate
division manually. So for now let's just lower the projection to add
support for it in lima.
In the future, an optimization pass may be implemented in lima to ensure
that both coords and projector come in the same register, then this
lowering may be disabled and in this case lima may use the built-in
projection and save the mul instruction from lowering.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-31 21:22:41 +02:00