Commit Graph

137083 Commits

Author SHA1 Message Date
Matt Turner efd1d5cc59 ci: Use CI_PROJECT_ROOT_NAMESPACE
Currently, the template in e.g. .gitlab-ci/deqp-runner.sh containing

    See https://$CI_PROJECT_NAMESPACE.pages.freedesktop.org/-/...

will print an invalid URL. Copied from .gitlab-ci/piglit/run.sh which
already uses CI_PROJECT_ROOT_NAMESPACE in its template.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9821>
2021-03-25 17:31:25 +00:00
Erik Faye-Lund 422ad76cca docs: Add 21.0.0 hashes
This was missed from the normal 21.0.0 release MR, so here's the hash
added retroactively.

Acked-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9826>
2021-03-25 17:26:54 +00:00
Eric Anholt b1e64a7771 ci/freedreno: Mark a630 as flaky on arb_draw_indirect-transform-feedback
This looks like a new one.  Unclear cause -- appeared in a large branch
with potential impact, but I had also been doing TF work around that time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9819>
2021-03-25 16:25:24 +00:00
Daniel Schürmann 8e43abcd2c aco/ra: remove exec handling for phis
These are not temporaries anymore.

Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Daniel Schürmann 3284f755a3 aco/ra: allow m0 in get_reg_specified()
Totals from 1 (0.00% of 136546) affected shaders (Navi10):
CodeSize: 12788 -> 12776 (-0.09%)
Instrs: 2441 -> 2438 (-0.12%)
Latency: 29713 -> 29731 (+0.06%)
InvThroughput: 14857 -> 14866 (+0.06%)
Copies: 354 -> 353 (-0.28%)
Branches: 66 -> 65 (-1.52%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Daniel Schürmann 4bfbd4de84 aco/ra: iterate backwards when coalescing phis
Aligning the phi definition with the operand from
the else- block can reduce the number of branches
if the else- block is otherwise empty.

Totals from 16 (0.01% of 136546) affected shaders (Navi10:
CodeSize: 707848 -> 707312 (-0.08%); split: -0.09%, +0.01%
Instrs: 126534 -> 126400 (-0.11%); split: -0.13%, +0.02%
Latency: 6399306 -> 6395082 (-0.07%)
InvThroughput: 6134374 -> 6132119 (-0.04%); split: -0.04%, +0.00%
SClause: 1879 -> 1871 (-0.43%)
Copies: 36316 -> 36219 (-0.27%); split: -0.37%, +0.10%
Branches: 4154 -> 4127 (-0.65%); split: -0.67%, +0.02%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Daniel Schürmann 7c64623e94 aco/ra: refactor SSA repairing during register allocation
The previous approach attempted to construct phi nodes
on-demand and on-the-fly. Due to several bugs, it became
necessary to always create incomplete phis for all live-in
variables on loop headers, which is highly inefficient.

The new approach assumes that live-in variables on loop-
headers don't get renamed, and afterwards does one renaming
pass per loop nest. This greatly simplifies the code and
reduces the memory footprint.

Totals from 37 (0.03% of 136546) affected shaders (Navi10):
CodeSize: 588148 -> 588020 (-0.02%); split: -0.03%, +0.01%
Instrs: 111793 -> 111761 (-0.03%); split: -0.04%, +0.01%
Latency: 4546013 -> 4545611 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 2806217 -> 2805730 (-0.02%); split: -0.03%, +0.01%
VClause: 2044 -> 2046 (+0.10%)
SClause: 3889 -> 3884 (-0.13%)
Copies: 17730 -> 17700 (-0.17%); split: -0.23%, +0.06%
Branches: 3282 -> 3280 (-0.06%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Daniel Schürmann 3ea2c05b32 aco/ra: split register_file initialization into separate function
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Daniel Schürmann e4902d4574 aco/ra: split affinity creation into separate function
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>
2021-03-25 15:12:19 +00:00
Erik Faye-Lund cf4ed05417 zink: follow spir-v 1.0 spec
OpEntryPoint is only supposed to include the Input and Output storage
classes prior to SPIR-V 1.4.

Since we're always emitting SPIR-V 1.0, we should simply omit these from
OpEntryPoint for now. If we start emitting SPIR-V 1.4 or later, we
should add these back in.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9828>
2021-03-25 14:29:48 +00:00
Erico Nunes ab71c0ba44 lima/ppir: rework liveness data structures to bitset
The liveness code in ppir can be a bottleneck in complicated shaders
with multiple spills, and the use of the mesa set data structure is one
of the main reasons it is expensive to run.
With some changes, it can be adapted to using bitsets which makes it run
substantially faster.
ppir liveness can't run with a regular bitset for registers since we
need to track inviditual component masks for non-ssa registers, but we
can switch to using a separate packed bit array just for the masks,
rather than a full blown hash set. This also makes operations such as
liveness propagation much more straightforward.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>
2021-03-25 14:17:26 +00:00
Erico Nunes 2b83d99538 lima/ppir: remove use of live_out
The live_out set was serving mostly as a temporary storage of data
propagated from the next instructions.
If we do an early copy to preserve the instruction live_in set and
propagate the liveness information directly to the live_in set, we can
skip having a live_out set entirely.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>
2021-03-25 14:17:26 +00:00
Erico Nunes 55b1dbb1c1 lima/ppir: remove liveness info from blocks
liveness information was stored in blocks so that the algorithm doesn't
have to find a valid instruction to inherit liveness information from.
It turns out this part of the code can be a performance bottleneck in
applications loading with complicated shaders, so skip the liveness
information in blocks to reduce the number of times we have to copy
liveness information.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>
2021-03-25 14:17:26 +00:00
Danylo Piliaiev 56909868cd turnip: implement VK_KHR_pipeline_executable_properties
Loosely based on ANV implementation.

For executable's internal representation we output:
- Initial NIR after spirv_to_nir
- Final optimized NIR
- IR3 disassembly

Note, that vkGetPipelineExecutablePropertiesKHR is required to
return executable properties even if pipeline was not created with
CAPTURE_STATISTICS or CAPTURE_INTERNAL_REPRESENTATIONS bits set.
So the executables array is unconditionally populated, however
NIR and IR3 disassemlies are filled only when
CAPTURE_INTERNAL_REPRESENTATIONS is set.

Passes dEQP-VK.pipeline.executable_properties.*
Works with RenderDoc.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>
2021-03-25 13:53:33 +00:00
Danylo Piliaiev 2bff8fd53b nir: add nir_shader_as_str function
It would be later used by Turnip in implementation of
VK_KHR_pipeline_executable_properties.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>
2021-03-25 13:53:33 +00:00
Icecream95 616394cf31 pan/mdg: Use appropriate sizes for global loads/stores
When always using 128-bit operations, an access at the end of an SSBO
could spill over to the next page and cause a GPU fault. To avoid
this, pick the smallest instruction that fits.

The if ladder might need extending for sizes of less than 32 bits, but
those currently fail in other parts of the compiler so are untested.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9747>
2021-03-25 13:23:47 +00:00
Icecream95 2f78ed8f0a pan/mdg: Rename load/store operations
Use the actual bit sizes the instructions deal with.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9747>
2021-03-25 13:23:47 +00:00
Rhys Perry b7fb5450ef ac: invalidate metadata after hs_emit_write_tess_factors()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9804>
2021-03-25 10:46:21 +00:00
Iago Toral Quiroga 22a979be65 broadcom/compiler: convert add to mul when possible to allow merge
Integer add/sub can be implemented as either an add or a mul instruction
but we always emit them as add instructions at VIR level. We can use this
flexibility to improve our QPU scheduling so we can be more effective
at instruction merging by converting these to mul instructions when we
are attempting to merge them with another add instruction.

total instructions in shared programs: 13721549 -> 13691004 (-0.22%)
instructions in affected programs: 3340493 -> 3309948 (-0.91%)
helped: 12805
HURT: 1656
Instructions are helped.

total max-temps in shared programs: 2319528 -> 2319317 (<.01%)
max-temps in affected programs: 5285 -> 5074 (-3.99%)
helped: 195
HURT: 3
Max-temps are helped.

total sfu-stalls in shared programs: 31616 -> 31752 (0.43%)
sfu-stalls in affected programs: 469 -> 605 (29.00%)
helped: 52
HURT: 161
Sfu-stalls are HURT.

total inst-and-stalls in shared programs: 13753165 -> 13722756 (-0.22%)
inst-and-stalls in affected programs: 3340383 -> 3309974 (-0.91%)
helped: 12782
HURT: 1666
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9769>
2021-03-25 09:51:42 +00:00
Alejandro Piñeiro bdf93f4e3b v3dv/cmd_buffer: return early for draw commands if there is nothing to draw
So for example, on v3dv_CmdDrawIndexed we can return early if
instanceCount is 0.

This fixes failures when using the simulator with tests with the
following pattern:
dEQP-VK.draw.instanced.draw_indexed_vk_primitive_topology*

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9820>
2021-03-25 09:38:04 +00:00
Iago Toral Quiroga bb201733ac v3dv/pipeline_cache: fix assert
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Fixes: e354c5280 ('3dv/pipeline: try to get the shader variant directly from the cache')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9824>
2021-03-25 09:25:27 +00:00
Erik Faye-Lund e87ff43fb3 zink: do not open-code vector-compares
We already have code to lower away these to something we don't need so
much special-case code to handle.

The sad part here is that we generate slightly worse code; trees of
OpLogicalAnd / OpLogicalOr instead of OpAny OpAll. But I would imagine
that for any GPU where this matters, these would be easy to combine
back, so I'm not losing a lot of sleep over this.

But this makes things simpler. And if we *really* care about OpAny or
OpAll, we should add NIR ALU instructions for them so we can optimize
them on other places as well, not open-code all places where it could
improve things.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>
2021-03-25 09:15:13 +00:00
Erik Faye-Lund 296a2fb350 zink: drop bool attempt in float vector compares
There's no such thing as a 1-bit float, so remove the special-case. It's
not going to trigger.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>
2021-03-25 09:15:13 +00:00
Erik Faye-Lund 9b52ac694c zink: fix vector comparison
This should have been using unordered compares all along.

This fixes a dEQP failure.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>
2021-03-25 09:15:13 +00:00
Vasily Khoruzhick bf09ba5385 lima: implement shader disk cache
Wire up disk cache routines and change fs and vs keys to use nir_sha1
instead of pointer to uncompiled shader to be able to reuse them for
disk cache.

Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>
2021-03-25 06:31:41 +00:00
Vasily Khoruzhick 3099ce7d02 lima: rename lima_{fs,vs}_bind_state to lima_{fs,vs}_uncompiled_shader
Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>
2021-03-25 06:31:41 +00:00
Vasily Khoruzhick 1261c06c68 lima: rename *_shader_state to *_compiled_shader
Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>
2021-03-25 06:31:41 +00:00
Tapani Pälli 5c7dd85e4f android: add some more stub functions for cross compilation
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9796>
2021-03-25 06:06:16 +00:00
Simon Ser e10a094e0a gbm: add gbm_bo_get_fd_for_plane
This commit adds a new gbm_bo_get_fd_for_plane function, which does the
same as gbm_bo_get_fd but allows specifying the plane.

v2: - Rename to gbm_bo_get_fd_for_plane (Emil)

Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5442>
2021-03-25 05:48:00 +00:00
Tomeu Vizoso ab7744b280 gallium/dri2: Pass the resource that corresponds to the plane
Previously, we were calling resource_get_handle for the first plane in
the image, regardless of what plane was being requested.

v2: - Add assert (Simon)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5442>
2021-03-25 05:48:00 +00:00
Tapani Pälli 382e5f2737 anv/android: fix image creation with external format
This fixes crashes seen with following group of tests:
   android.graphics.cts.BasicVulkanGpuTest

Fixes: 6fa56273be ("anv/image: Drop duplicate 'format' in anv_image_create()")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9799>
2021-03-25 07:33:38 +02:00
Jesse Schwartzentruber 02492bea5f glcpp: Fix undefined behaviour in glcpp
Specifically, fix this error (which is covered in existing tests):

    ../src/compiler/glsl/glcpp/pp.c:198:28: runtime error: applying non-zero offset 1 to null pointer
    SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../src/compiler/glsl/glcpp/pp.c:198:28 in

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9669>
2021-03-25 00:23:43 +00:00
Dylan Baker 95c58aacf8 docs: update calendar and link releases notes for 21.0.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Dylan Baker 38bce7238c docs: Add 21.0.1 hashes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Dylan Baker e26906ce93 docs: add release notes for 21.0.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Dylan Baker 3e9d753cb9 docs: update calendar and link releases notes for 20.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Dylan Baker 8463066078 docs: Add hashes for 20.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Dylan Baker 930d2a92a3 docs: add release notes for 20.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>
2021-03-25 00:18:57 +00:00
Mike Blumenkrantz e20aebb83c lavapipe: use the passed offset for CmdCopyQueryPoolResults
this avoids overwriting buffer[0] on every copy

Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9813>
2021-03-25 00:07:03 +00:00
Mike Blumenkrantz 4ad5bfd1bd lavapipe: fix CmdCopyQueryPoolResults for partial pipeline statistics queries
if this isn't a query for all pipeline statistics, the bits that are
set need to be individually copied in increasing order

Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9813>
2021-03-25 00:07:03 +00:00
Mike Blumenkrantz 5ecad3cb44 util/set: stop leaking u32 key sets which pass a mem ctx
Fixes: 10a7682413 ("util: add _mesa_set_create_u32_keys where keys are not pointers")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9810>
2021-03-24 23:32:40 +00:00
Caio Marcelo de Oliveira Filho e93c8ab023 intel/compiler: Use a struct for brw_compile_cs parameters
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 05933fb0f7 intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders
Make INTEL_DEBUG=blorp dump the blorp shaders instead using the
general INTEL_DEBUG=fs,vs, which is now reserved to the actual FS and
VS shaders used by the pipeline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 7fb1e58651 intel/compiler: Make visitors take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 758eb18c6f intel/compiler: Make vec4 generator take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 244d2daa00 intel/compiler: Make brw_postprocess_nir take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 82d77f0ea8 intel/compiler: Refactor the shader INTEL_DEBUG checks
Make the check once in a variable, that can be reused for other parts.
Also add `unlikely` to the various conditionals depending on it

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 57d664245e intel/compiler: Use a struct for brw_compile_vs parameters
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho f5e1765f98 intel/compiler: Use a struct for brw_compile_fs parameters
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 84c3d68344 intel/compiler: Make vue_map parameter const for brw_compile_fs
Just a documentation hint that the VUE map is not modified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00