intel/compiler: Make brw_postprocess_nir take debug_enabled as a parameter

The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
This commit is contained in:
Caio Marcelo de Oliveira Filho 2021-03-23 11:08:32 -07:00 committed by Marge Bot
parent 82d77f0ea8
commit 244d2daa00
7 changed files with 10 additions and 11 deletions

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@ -9093,7 +9093,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
if (!key->multisample_fbo)
NIR_PASS_V(nir, brw_nir_demote_sample_qualifiers);
NIR_PASS_V(nir, brw_nir_move_interpolation_to_top);
brw_postprocess_nir(nir, compiler, true);
brw_postprocess_nir(nir, compiler, true, debug_enabled);
brw_nir_populate_wm_prog_data(nir, compiler->devinfo, key, prog_data);
@ -9420,7 +9420,7 @@ compile_cs_to_nir(const struct brw_compiler *compiler,
NIR_PASS_V(shader, nir_opt_constant_folding);
NIR_PASS_V(shader, nir_opt_dce);
brw_postprocess_nir(shader, compiler, true);
brw_postprocess_nir(shader, compiler, true, debug_enabled);
return shader;
}
@ -9721,7 +9721,7 @@ brw_compile_bs(const struct brw_compiler *compiler, void *log_data,
const unsigned max_dispatch_width = 16;
brw_nir_apply_key(shader, compiler, &key->base, max_dispatch_width, true);
brw_postprocess_nir(shader, compiler, true);
brw_postprocess_nir(shader, compiler, true, debug_enabled);
fs_visitor *v = NULL, *v8 = NULL, *v16 = NULL;
bool has_spilled = false;

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@ -1077,11 +1077,9 @@ nir_shader_has_local_variables(const nir_shader *nir)
*/
void
brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
bool is_scalar)
bool is_scalar, bool debug_enabled)
{
const struct gen_device_info *devinfo = compiler->devinfo;
bool debug_enabled =
(INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->info.stage));
UNUSED bool progress; /* Written by OPT */

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@ -134,7 +134,8 @@ bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
void brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
bool is_scalar);
bool is_scalar,
bool debug_enabled);
bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);

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@ -1323,7 +1323,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_lower_tes_inputs(nir, input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, is_scalar);
brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
nir->info.outputs_written,

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@ -2866,7 +2866,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
brw_nir_lower_vs_inputs(nir, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, is_scalar);
brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
prog_data->base.clip_distance_mask =
((1 << nir->info.clip_distance_array_size) - 1);

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@ -617,7 +617,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
brw_nir_lower_vue_inputs(nir, &c.input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, is_scalar);
brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
prog_data->base.clip_distance_mask =
((1 << nir->info.clip_distance_array_size) - 1);

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@ -390,7 +390,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
if (key->quads_workaround)
brw_nir_apply_tcs_quads_workaround(nir);
brw_postprocess_nir(nir, compiler, is_scalar);
brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled);
bool has_primitive_id =
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);