73c82570cb
radeonsi: move setting one GS shader key field out of si_shader_selector_key
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
99c5e03986
radeonsi: move setting most TCS shader key fields out of si_shader_selector_key
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
dba914de85
radeonsi: unroll loops in si_emit_spi_map using 33 C++ template instantiations
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
3ea3621b8d
radeonsi: determine num_vbos_in_user_sgprs from template arguments in draw_vbo
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
7a20110ad3
radeonsi: precompute si_vgt_stages_key for NGG in si_shader
...
to remove this overhead from si_update_shaders
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
70220a1896
radeonsi: check flatshade and sprite_coord_enable for spi_map in bind_rs_state
...
it doesn't need to be in si_update_shaders
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
98d07e1928
radeonsi: make si_update_shaders a C++ template in si_state_draw.cpp
...
This reduces driver overhead.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
76fe6a0242
radeonsi: move PS inputs_read computation out of si_get_vs_key_outputs
...
to reduce overhead of si_update_shaders
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
6d1ab77a8f
radeonsi: rewrite inlinable uniform states for shader keys in si_context
...
directly update the shader keys in si_context
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343 >
2021-09-14 15:24:11 +00:00
0e64252912
radeonsi: add AMD_DEBUG=ib to print IBs
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812 >
2021-09-10 23:32:03 +00:00
576f8394db
radeonsi: remove the primitive discard compute shader
...
It doesn't always work, it's only useful on gfx9 and older, and it's too
complicated.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4011
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812 >
2021-09-10 23:32:03 +00:00
34a2c75310
radeonsi: enable DCC stores on gfx10.3 APUs for better performance
...
There is just one hw bug that we need to handle.
NO_DCC_FB was unused.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449 >
2021-09-01 07:51:30 +00:00
8c845d4cb4
radeonsi: rename DCC_WRITE -> ALLOW_DCC_STORE
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449 >
2021-09-01 07:51:30 +00:00
6cb2f07e90
radeonsi: add si_print_current_ib function for debugging
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656 >
2021-09-01 00:42:58 +00:00
9fb77745f5
radeonsi: inline si_need_gfx_cs_space
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656 >
2021-09-01 00:42:58 +00:00
b15c413947
radeonsi: simplify memory usage checking by merging vram and gtt counters
...
no change in behavior
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656 >
2021-09-01 00:42:58 +00:00
c005b2cd4b
radeonsi: move as_ls/es/ngg setting out of si_shader_selector_key
...
Do it when we bind shaders.
The advantages are:
- no need to memset the fields when any shader variant state is changed
(e.g. culling on/off)
- no need to recompute the fields every time that happens
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656 >
2021-09-01 00:42:57 +00:00
08310f85ae
radeonsi: remove instancing support from the prim discard compute shader
...
It's not important for workstation apps on Vega.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656 >
2021-09-01 00:42:57 +00:00
10a46226b1
gallium: remove vertices_per_patch, add pipe_context::set_patch_vertices
...
We would like draw-only display lists to have immutable draw info and
this is the only GL non-draw state in pipe_draw_info (not counting
view_mask).
It also allows removing some code from draw_vbo for tessellation.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351 >
2021-08-21 00:08:11 +00:00
6fc38d3b07
radeonsi: allow arbitrary swizzle modes for displayable DCC
...
by adding retile shader variants
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430 >
2021-08-20 14:28:36 +00:00
59fe704c45
gallium: simplify VRAM uploads by adding PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY
...
When this flag is set, u_threaded_context will try not to map it directly
for better buffer placement. It's set by drivers when visible VRAM is too
small.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12257 >
2021-08-09 11:58:48 +00:00
6546f28cc8
radeonsi: drop smoothing quality to 4xAA for better performance
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754 >
2021-07-08 18:37:41 +00:00
b141e50282
radeonsi: add optimal multi draws and draw-level splitting for prim discard CS
...
This is a partial rewrite of some parts of the code.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11510 >
2021-06-28 13:23:14 +00:00
9fa0d2cf35
radeonsi: change how the prim discard CS is enabled and splitting limits
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11510 >
2021-06-28 13:23:14 +00:00
06da711350
radeonsi: remove the GDS variants of compute-based primitive discard
...
The GDS ordered append variant is unstable due to kernel and firmware bugs.
The unordered GDS variant isn't faster than the memory-based variant.
Only the memory-based variant is kept.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11510 >
2021-06-28 13:23:14 +00:00
a448074d05
radeonsi: don't compile TES and GS draw_vbo variants for the prim discard CS
...
This also fixes the incorrect emit_draw_packets template argument.
The condition should be inverted.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11102 >
2021-06-21 19:03:29 +00:00
72a395b6de
radeonsi: remove the chip_class dimension from the draw_vbo array
...
We don't use/initialize draw_vbo callbacks for other generations anymore.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384 >
2021-06-16 21:29:13 +00:00
24895f020a
radeonsi: move a few functions from si_state_draw.cpp into si_gfx_cs.c
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384 >
2021-06-16 21:29:13 +00:00
83250036be
radeonsi/nir: add si_nir_is_output_const_if_tex_is_const
...
Determine if a given shader write the same constant value to its output
if a specific input texture is replaced by constant load.
It's done by checking if the store_output intrinsics only depends on
constant and a texture. If it's true, the given texture is replaced by
a constant load in cloned shader and this clone is optimized.
Then the output is checked (= is it constant or not).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979 >
2021-06-15 11:18:02 +02:00
b2bd9c5ccd
radeonsi: add si_install_draw_wrapper
...
This allows to implement custom draw_vbo code-path without
touching si_draw_vbo.
As an example, skipped all draw calls with an odd new_draws
could be done like this:
void mywrapper(...) {
if (new_draws % 2)
return;
return sctx->real_draw_vbo(...);
}
if (some_condition_is_met)
si_install_draw_wrapper(sctx, mywrapper);
Instead of having to add the "if ()" condition inside si_draw_vbo.
Note that a single wrapper may be installed so care must be taken
to not override an existing wrapper.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979 >
2021-06-15 10:19:04 +02:00
ff8a930cf7
radeonsi: add _once suffix to depth_cleared_level_mask
...
And add a new variable to disambiguate between "has been cleared once" and
"is cleared".
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979 >
2021-06-15 10:19:02 +02:00
74abd5df0e
aux/tc: pass rebind count and rebind bitmask with replace_buffer_storage func
...
tc already calculates all the rebinding that needs to be done on a given
context, so (some of) this info can be passed on to drivers to enable
optimizations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11245 >
2021-06-14 20:42:47 +00:00
7844bdadac
radeonsi: remove DFSM after we discovered how bad it is
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
9ba17ec21a
radeonsi: generate buffer_id_unique for u_threaded_context
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
9dc7fff448
radeonsi: allow changing the NGG subgroup size to 256 but don't change it yet
...
Currently, 128 seems to have the best performance.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
712f74f590
radeonsi: remove 8 bytes from si_resource, turn other 4 bytes into padding
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
5af124c92c
radeonsi: change si_resource::alignment to alignment_log2 for better packing
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
36e07198a7
radeonsi: always use the L2 LRU cache policy for faster clears and copies
...
Waves and CP DMA can finish sooner if L2 doesn't do any evictions, which
is hard to predict.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
c7e731c737
radeonsi: remove unused SI_IMAGE_ACCESS_AS_BUFFER
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
94a1f45e15
ac/llvm: set target features per function instead of per target machine
...
This is a cleanup that allows the removal of the wave32 target machine and
the wave32 pass manager.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813 >
2021-05-25 16:15:44 +00:00
b04044b350
radeonsi: stop using u_resource_vtbl::resource_destroy
...
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10659 >
2021-05-21 17:38:04 +00:00
ec77a2d43a
gallium/u_threaded: add callbacks and documentation for resource busy checking
...
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10662 >
2021-05-17 10:37:24 +00:00
967757a208
gallium+(u_threaded,r300,r600,radeonsi): move transfer offset into pipe_transfer
...
Let's use the 4 bytes of unused padding usefully in pipe_transfer.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527 >
2021-05-01 17:38:42 +00:00
dae3113c3d
gallium: split drawid out of pipe_draw_info and as a separate draw_vbo param
...
the only case in which this is nonzero is if a multidraw gets split by the frontend,
i.e., mesa core, and in all other cases it can be ignored. the value can also be ignored
for all indirect draws, though it seems many (most?) gallium drivers are not aware of this
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166 >
2021-04-30 03:59:19 +00:00
4566383ae4
gallium: move pipe_draw_info::index_bias to pipe_draw_start_count_bias
...
this moves index_bias into the multidraw struct, enabling draws where the value
changes to be merged; the draw_info struct member is renamed and moved to the end
of the struct for tc use
u_vbuf still has some checks to split draws if index_bias changes, maybe
this can be removed at some point?
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166 >
2021-04-30 03:59:19 +00:00
4fe6c85526
gallium: rename pipe_draw_start_count -> pipe_draw_start_count_bias
...
and add an index_bias member
no functional changes yet, just the rename and unused struct member
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166 >
2021-04-30 03:59:19 +00:00
804e292440
radeonsi: remove the separate DCC optimization for Stoney
...
This removes some complexity from the driver.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10343 >
2021-04-26 22:53:30 +00:00
1f8fa96412
radeonsi: make the gfx9 DCC MSAA clear shader depend on the number of samples
...
because different DCC equations are used.
Fixes: 3120113ee7https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10343 >
2021-04-26 22:53:30 +00:00
4a6b87ceab
radeonsi: implement pipe_context.create_video_buffer_with_modifiers
...
Just pass down the modifier list to vl_video_buffer_create_as_resource,
filtering out DCC modifiers because we don't support these for now.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10237 >
2021-04-22 15:57:29 +00:00
a1653854f5
radeonsi: fix automatic DCC retiling after compute image stores
...
Only internal compute shaders use DCC stores, so the TODOs are not
critical yet.
Fixes: 1d64a1045ehttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261 >
2021-04-17 02:37:49 +00:00
Marek Olšák
Pierre-Eric Pelloux-Prayer
Mike Blumenkrantz
Simon Ser