radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
MSAA 4x and 8x should only clear the first 2 samples because other samples are uncompressed. The compute shader only clears that subset of DCC. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
This commit is contained in:
Marek Olšák
Marge Bot
parent
8b95f51ef1
commit
3120113ee7
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@ -255,6 +255,13 @@ static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE
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addr = gfx9_dcc_addr_from_coord(info, &dout, dout.metaBlkWidth, dout.metaBlkHeight,
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dout.metaBlkDepth, dout.pitch, dout.height,
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in.x, in.y, in.slice, in.sample, in.pipeXor);
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if (in.sample == 1) {
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/* Sample 0 should be one byte before sample 1. The DCC MSAA clear relies on it. */
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assert(addr - 1 ==
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gfx9_dcc_addr_from_coord(info, &dout, dout.metaBlkWidth, dout.metaBlkHeight,
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dout.metaBlkDepth, dout.pitch, dout.height,
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in.x, in.y, in.slice, 0, in.pipeXor));
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}
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} else {
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addr = gfx10_dcc_addr_from_coord(info, dout.equation.gfx10_bits,
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in.bpp, dout.metaBlkWidth, dout.metaBlkHeight,
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@ -43,6 +43,7 @@ void si_init_buffer_clear(struct si_clear_info *info,
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info->size = size;
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info->clear_value = clear_value;
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info->writemask = 0xffffffff;
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info->is_dcc_msaa = false;
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}
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static void si_init_buffer_clear_rmw(struct si_clear_info *info,
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@ -75,6 +76,12 @@ void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
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/* Execute clears. */
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for (unsigned i = 0; i < num_clears; i++) {
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if (info[i].is_dcc_msaa) {
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gfx9_clear_dcc_msaa(sctx, info[i].resource, info[i].clear_value,
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SI_OP_SKIP_CACHE_INV_BEFORE, SI_COHERENCY_CP);
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continue;
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}
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assert(info[i].size > 0);
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if (info[i].writemask != 0xffffffff) {
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@ -328,10 +335,13 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi
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if (tex->buffer.b.b.last_level > 0)
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return false;
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/* 4x and 8x MSAA needs a sophisticated compute shader for
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* the clear. See AMDVLK. */
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if (tex->buffer.b.b.nr_storage_samples >= 4)
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return false;
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/* 4x and 8x MSAA need to clear only sample 0 and 1 in a compute shader and leave other
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* samples untouched. (only the first 2 samples are compressed) */
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if (tex->buffer.b.b.nr_storage_samples >= 4) {
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si_init_buffer_clear(out, dcc_buffer, 0, 0, clear_value);
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out->is_dcc_msaa = true;
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return true;
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}
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clear_size = tex->surface.meta_size;
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} else {
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@ -725,6 +725,78 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
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pipe_resource_reference(&saved_sb.buffer, NULL);
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}
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void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
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unsigned flags, enum si_coherency coher)
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{
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struct pipe_context *ctx = &sctx->b;
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struct si_texture *tex = (struct si_texture*)res;
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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/* Save states. */
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void *saved_cs = sctx->cs_shader_state.program;
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struct pipe_shader_buffer saved_sb = {};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb);
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unsigned saved_writable_mask = 0;
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(0)))
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saved_writable_mask |= 1 << 0;
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/* Set the DCC buffer. */
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assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX);
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assert(tex->buffer.bo_size <= UINT_MAX);
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struct pipe_shader_buffer sb = {};
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sb.buffer = &tex->buffer.b.b;
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sb.buffer_offset = tex->surface.meta_offset;
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sb.buffer_size = tex->buffer.bo_size - sb.buffer_offset;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &sb, 0x1);
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sctx->cs_user_data[0] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) |
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(tex->surface.u.gfx9.color.dcc_height << 16);
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sctx->cs_user_data[1] = (clear_value & 0xffff) |
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((uint32_t)tex->surface.tile_swizzle << 16);
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/* These variables identify the shader variant. */
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unsigned swizzle_mode = tex->surface.u.gfx9.swizzle_mode;
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unsigned bpe_log2 = util_logbase2(tex->surface.bpe);
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bool samples8 = tex->buffer.b.b.nr_storage_samples == 8;
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bool is_array = tex->buffer.b.b.array_size > 1;
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void **shader = &sctx->cs_clear_dcc_msaa[swizzle_mode][bpe_log2][samples8][is_array];
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if (!*shader)
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*shader = gfx9_create_clear_dcc_msaa_cs(sctx, tex);
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ctx->bind_compute_state(ctx, *shader);
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/* Dispatch compute. */
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unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width);
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unsigned height = DIV_ROUND_UP(tex->buffer.b.b.height0, tex->surface.u.gfx9.color.dcc_block_height);
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unsigned depth = DIV_ROUND_UP(tex->buffer.b.b.array_size, tex->surface.u.gfx9.color.dcc_block_depth);
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struct pipe_grid_info info = {};
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info.block[0] = 8;
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info.block[1] = 8;
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info.block[2] = 1;
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info.last_block[0] = width % info.block[0];
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info.last_block[1] = height % info.block[1];
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info.grid[0] = DIV_ROUND_UP(width, info.block[0]);
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info.grid[1] = DIV_ROUND_UP(height, info.block[1]);
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info.grid[2] = depth;
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si_launch_grid_internal(sctx, &info, saved_cs, flags);
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enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, tex->surface.meta_size);
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if (flags & SI_OP_SYNC_AFTER)
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sctx->flags |= cache_policy == L2_BYPASS ? SI_CONTEXT_WB_L2 : 0;
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/* Restore states. */
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb, saved_writable_mask);
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pipe_resource_reference(&saved_sb.buffer, NULL);
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}
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/* Expand FMASK to make it identity, so that image stores can ignore it. */
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void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex)
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{
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@ -268,6 +268,17 @@ static void si_destroy_context(struct pipe_context *context)
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}
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}
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for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_clear_dcc_msaa); i++) {
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for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i]); j++) {
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for (unsigned k = 0; k < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j]); k++) {
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for (unsigned l = 0; l < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j][k]); l++) {
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if (sctx->cs_clear_dcc_msaa[i][j][k][l])
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sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_dcc_msaa[i][j][k][l]);
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}
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}
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}
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}
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if (sctx->blitter)
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util_blitter_destroy(sctx->blitter);
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@ -1316,6 +1316,10 @@ struct si_context {
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bool thread_trace_enabled;
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unsigned context_flags;
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/* Shaders. */
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/* TODO: move other shaders here too */
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void *cs_clear_dcc_msaa[32][5][2][2]; /* [swizzle_mode][log2(bpe)][samples == 8][is_array] */
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};
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/* si_blit.c */
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@ -1368,6 +1372,7 @@ struct si_clear_info {
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uint32_t size;
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uint32_t clear_value;
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uint32_t writemask;
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bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */
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};
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enum pipe_format si_simplify_cb_format(enum pipe_format format);
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@ -1423,6 +1428,8 @@ void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surfac
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unsigned dsty, unsigned width, unsigned height,
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bool render_condition_enabled);
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void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
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void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
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unsigned flags, enum si_coherency coher);
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void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
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void si_init_compute_blit_functions(struct si_context *sctx);
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@ -1539,6 +1546,7 @@ void si_resume_queries(struct si_context *sctx);
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/* si_shaderlib_nir.c */
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void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
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void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
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/* si_shaderlib_tgsi.c */
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void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
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@ -100,3 +100,49 @@ void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf)
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return create_nir_cs(sctx, &b);
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}
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void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex)
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{
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const nir_shader_compiler_options *options =
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sctx->b.screen->get_compiler_options(sctx->b.screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE);
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nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, options, "clear_dcc_msaa");
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b.shader->info.cs.local_size[0] = 8;
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b.shader->info.cs.local_size[1] = 8;
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b.shader->info.cs.local_size[2] = 1;
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b.shader->info.cs.user_data_components_amd = 2;
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b.shader->info.num_ssbos = 1;
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/* Get user data SGPRs. */
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nir_ssa_def *user_sgprs = nir_load_user_data_amd(&b);
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nir_ssa_def *dcc_pitch, *dcc_height, *clear_value, *pipe_xor;
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unpack_2x16(&b, nir_channel(&b, user_sgprs, 0), &dcc_pitch, &dcc_height);
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unpack_2x16(&b, nir_channel(&b, user_sgprs, 1), &clear_value, &pipe_xor);
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clear_value = nir_u2u16(&b, clear_value);
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/* Get the 2D coordinates. */
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nir_ssa_def *coord = get_global_ids(&b, 3);
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nir_ssa_def *zero = nir_imm_int(&b, 0);
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/* Multiply the coordinates by the DCC block size (they are DCC block coordinates). */
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coord = nir_imul(&b, coord,
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nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width,
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tex->surface.u.gfx9.color.dcc_block_height,
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tex->surface.u.gfx9.color.dcc_block_depth, 0), 0x7));
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nir_ssa_def *offset =
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ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe,
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&tex->surface.u.gfx9.color.dcc_equation,
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dcc_pitch, dcc_height, zero, /* DCC slice size */
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nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), /* x, y */
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tex->buffer.b.b.array_size > 1 ? nir_channel(&b, coord, 2) : zero, /* z */
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zero, pipe_xor); /* sample, pipe_xor */
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/* The trick here is that DCC elements for an even and the next odd sample are next to each other
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* in memory, so we only need to compute the address for sample 0 and the next DCC byte is always
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* sample 1. That's why the clear value has 2 bytes - we're clearing 2 samples at the same time.
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*/
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nir_store_ssbo(&b, clear_value, zero, offset, .write_mask=0x1, .align_mul=2);
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return create_nir_cs(sctx, &b);
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}
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