We'll open up a union for class specific data, since this is interesting
only to BI_MINMAX. (And even then...)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
I don't want to have 20 class-specific structures floating around. So
let's derive them all from a common generic ALU type.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
...along with some helpers to generate indices. The indexing scheme is
mostly a copypaste from Midgard, except we specifically reserve 0 as the
sentinel (midgard uses ~0 for this which has always been a pain point).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
We're making some pretty dramatic design pivots so this early on it'll
be easier to start from scratch, I think.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
These run on the ADD unit and evidently need to be their own clause
(probably treated as a high-latency instruction). Like csel, they can
either do a float comparison directly or ingest a 0/1 value.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
Currently the schedule_program implementation being used is picked
at compile time, which on the Android platform means that the
bifrost compiler & scheduler is used for all targets, including
midgard based hardware.
This commit disambiguates between the two schedule_program functions.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Set of opcodes doesn't have enough flexibility in certain cases. E.g.
Utgard PP has vector conditional select operation, but condition is always
scalar. Lowering all the vector selects to scalar increases instruction
number, so we need a way to filter only those ops that can't be handled
in hardware.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Panfrost is the only user of the macro; we are better off expanding than
having random stuff in nir.h.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This path shouldn't be possible for in-spec shaders, but let's be
defensive. (Because security, right? Mostly because Coverity.)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes errors for some people building Mesa:
../src/panfrost/bifrost/bifrost_sched.c:32:31: error: initializer
element is not constant
const unsigned max_vec2_reg = max_primary_reg / 2;
../src/panfrost/bifrost/bifrost_sched.c:33:31: error: initializer
element is not constant
const unsigned max_vec3_reg = max_primary_reg / 4; // XXX: Do we need
to align vec3 to vec4 boundary?
../src/panfrost/bifrost/bifrost_sched.c:34:31: error: initializer
element is not constant
const unsigned max_vec4_reg = max_primary_reg / 4;
../src/panfrost/bifrost/bifrost_sched.c:35:32: error: initializer
element is not constant
const unsigned max_registers = max_primary_reg +
../src/panfrost/bifrost/bifrost_sched.c:40:28: error: initializer
element is not constant
const unsigned vec2_base = primary_base + max_primary_reg;
../src/panfrost/bifrost/bifrost_sched.c:41:28: error: initializer
element is not constant
const unsigned vec3_base = vec2_base + max_vec2_reg;
../src/panfrost/bifrost/bifrost_sched.c:42:28: error: initializer
element is not constant
const unsigned vec4_base = vec3_base + max_vec3_reg;
../src/panfrost/bifrost/bifrost_sched.c:43:27: error: initializer
element is not constant
const unsigned vec4_end = vec4_base + max_vec4_reg;
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
We don't actually have a standalone compiler in-tree yet, but let's get
prepared for when we do.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
The disassembler was updated to move common code with the compiler into
a shared header. Additional, some new ops and control registers relating
to rounding were added.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
In preparation for a Panfrost-based non-Gallium driver (maybe
Vulkan...?), hoist everything except for the Gallium driver into a
shared src/panfrost. Practically, that means the compilers, the headers,
and pandecode.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig
Eric Anholt
Icecream95
Robert Foss
Vasily Khoruzhick