pan/bifrost: Check in remainder of the Bifrost compiler
What it says on the tin. Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
parent
0e126aa0f0
commit
b93fa7d232
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/*
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* Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "bifrost_opts.h"
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#include "compiler_defines.h"
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bool
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bifrost_opt_branch_fusion(compiler_context *ctx, bifrost_block *block)
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{
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bool progress = false;
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mir_foreach_instr_in_block_safe(block, instr) {
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if (instr->op != op_branch) continue;
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if (instr->literal_args[0] != BR_COND_EQ) continue;
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unsigned src1 = instr->ssa_args.src0;
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// Only work on SSA values
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if (src1 >= SSA_FIXED_MINIMUM) continue;
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// Find the source for this conditional branch instruction
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// It'll be a CSEL instruction
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// If it's comparision is one of the ops that our conditional branch supports
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// then we can merge the two
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mir_foreach_instr_in_block_from_rev(block, next_instr, instr) {
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if (next_instr->op != op_csel_i32) continue;
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if (next_instr->ssa_args.dest == src1) {
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// We found the CSEL instruction that is the source here
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// Check its condition to make sure it matches what we can fuse
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unsigned cond = next_instr->literal_args[0];
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if (cond == CSEL_IEQ) {
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// This CSEL is doing an IEQ for our conditional branch doing EQ
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// We can just emit a conditional branch that does the comparison
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struct bifrost_instruction new_instr = {
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.op = op_branch,
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.dest_components = 0,
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.ssa_args = {
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.dest = SSA_INVALID_VALUE,
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.src0 = next_instr->ssa_args.src0,
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.src1 = next_instr->ssa_args.src1,
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.src2 = SSA_INVALID_VALUE,
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.src3 = SSA_INVALID_VALUE,
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},
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.literal_args[0] = BR_COND_EQ,
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.literal_args[1] = instr->literal_args[1],
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};
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mir_insert_instr_before(instr, new_instr);
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mir_remove_instr(instr);
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progress |= true;
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break;
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}
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}
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}
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}
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return progress;
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}
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@ -0,0 +1,33 @@
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/*
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* Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef bifrost_opts_h
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#define bifrost_opts_h
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#include "compiler_defines.h"
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#include <stdbool.h>
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bool
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bifrost_opt_branch_fusion(compiler_context *ctx, bifrost_block *block);
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#endif /* bifrost_opts_h */
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@ -0,0 +1,398 @@
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/*
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* Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "util/register_allocate.h"
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#include "compiler_defines.h"
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#include "bifrost_sched.h"
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#include "bifrost_compile.h"
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#include "bifrost_print.h"
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#define BI_DEBUG
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const unsigned max_primary_reg = 64; // XXX: Not correct since there are special ones in the top end
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const unsigned max_vec2_reg = max_primary_reg / 2;
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const unsigned max_vec3_reg = max_primary_reg / 4; // XXX: Do we need to align vec3 to vec4 boundary?
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const unsigned max_vec4_reg = max_primary_reg / 4;
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const unsigned max_registers = max_primary_reg +
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max_vec2_reg +
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max_vec3_reg +
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max_vec4_reg;
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const unsigned primary_base = 0;
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const unsigned vec2_base = primary_base + max_primary_reg;
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const unsigned vec3_base = vec2_base + max_vec2_reg;
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const unsigned vec4_base = vec3_base + max_vec3_reg;
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const unsigned vec4_end = vec4_base + max_vec4_reg;
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static unsigned
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find_or_allocate_temp(compiler_context *ctx, unsigned hash)
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{
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if (hash >= SSA_FIXED_MINIMUM)
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return hash;
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unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(ctx->hash_to_temp, hash + 1);
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if (temp)
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return temp - 1;
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/* If no temp is find, allocate one */
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temp = ctx->num_temps++;
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ctx->max_hash = MAX2(ctx->max_hash, hash);
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_mesa_hash_table_u64_insert(ctx->hash_to_temp, hash + 1, (void *) ((uintptr_t) temp + 1));
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return temp;
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}
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static bool
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is_live_in_instr(bifrost_instruction *instr, unsigned temp)
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{
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if (instr->ssa_args.src0 == temp) return true;
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if (instr->ssa_args.src1 == temp) return true;
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if (instr->ssa_args.src2 == temp) return true;
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if (instr->ssa_args.src3 == temp) return true;
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return false;
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}
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static bool
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is_live_after_instr(compiler_context *ctx, bifrost_block *blk, bifrost_instruction *instr, unsigned temp)
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{
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// Scan forward in the block from this location to see if we are still live.
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mir_foreach_instr_in_block_from(blk, ins, mir_next_instr(instr)) {
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if (is_live_in_instr(ins, temp))
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return true;
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}
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// XXX: Walk all successor blocks and ensure the value isn't used there
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return false;
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}
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static uint32_t
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ra_select_callback(struct ra_graph *g, BITSET_WORD *regs, void *data)
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{
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for (int i = primary_base; i < vec4_end; ++i) {
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if (BITSET_TEST(regs, i)) {
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return i;
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}
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}
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assert(0);
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return 0;
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}
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static uint32_t
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ra_get_phys_reg(compiler_context *ctx, struct ra_graph *g, unsigned temp, unsigned max_reg)
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{
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if (temp == SSA_INVALID_VALUE ||
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temp >= SSA_FIXED_UREG_MINIMUM ||
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temp == SSA_FIXED_CONST_0)
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return temp;
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if (temp >= SSA_FIXED_MINIMUM)
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return SSA_REG_FROM_FIXED(temp);
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assert(temp < max_reg);
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uint32_t r = ra_get_node_reg(g, temp);
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if (r >= vec4_base)
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return (r - vec4_base) * 4;
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else if (r >= vec3_base)
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return (r - vec3_base) * 4;
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else if (r >= vec2_base)
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return (r - vec2_base) * 2;
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return r;
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}
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static void
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allocate_registers(compiler_context *ctx)
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{
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struct ra_regs *regs = ra_alloc_reg_set(NULL, max_registers, true);
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int primary_class = ra_alloc_reg_class(regs);
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int vec2_class = ra_alloc_reg_class(regs);
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int vec3_class = ra_alloc_reg_class(regs);
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int vec4_class = ra_alloc_reg_class(regs);
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// Allocate our register classes and conflicts
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{
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unsigned reg = 0;
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unsigned primary_base = 0;
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// Add all of our primary scalar registers
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for (unsigned i = 0; i < max_primary_reg; ++i) {
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ra_class_add_reg(regs, primary_class, reg);
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reg++;
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}
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// Add all of our vec2 class registers
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// These alias with the scalar registers
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for (unsigned i = 0; i < max_vec2_reg; ++i) {
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ra_class_add_reg(regs, vec2_class, reg);
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// Tell RA that this conflicts with primary class registers
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// Make sure to tell the RA utility all conflict slots
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ra_add_reg_conflict(regs, reg, primary_base + i*2 + 0);
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ra_add_reg_conflict(regs, reg, primary_base + i*2 + 1);
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reg++;
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}
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// Add all of our vec3 class registers
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// These alias with the scalar registers
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for (unsigned i = 0; i < max_vec3_reg; ++i) {
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ra_class_add_reg(regs, vec3_class, reg);
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// Tell RA that this conflicts with primary class registers
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// Make sure to tell the RA utility all conflict slots
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// These are aligned to vec4 even though they only conflict with a vec3 wide slot
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 0);
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 1);
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 2);
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// State that this class conflicts with the vec2 class
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ra_add_reg_conflict(regs, reg, vec2_base + i*2 + 0);
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ra_add_reg_conflict(regs, reg, vec2_base + i*2 + 1);
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reg++;
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}
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// Add all of our vec4 class registers
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// These alias with the scalar registers
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for (unsigned i = 0; i < max_vec4_reg; ++i) {
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ra_class_add_reg(regs, vec4_class, reg);
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// Tell RA that this conflicts with primary class registers
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// Make sure to tell the RA utility all conflict slots
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// These are aligned to vec4 even though they only conflict with a vec3 wide slot
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 0);
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 1);
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 2);
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ra_add_reg_conflict(regs, reg, primary_base + i*4 + 3);
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// State that this class conflicts with the vec2 class
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ra_add_reg_conflict(regs, reg, vec2_base + i*2 + 0);
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ra_add_reg_conflict(regs, reg, vec2_base + i*2 + 1);
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// State that this class conflicts with the vec3 class
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// They conflict on the exact same location due to alignments
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ra_add_reg_conflict(regs, reg, vec3_base + i);
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reg++;
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}
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}
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ra_set_finalize(regs, NULL);
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mir_foreach_block(ctx, block) {
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mir_foreach_instr_in_block(block, instr) {
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instr->ssa_args.src0 = find_or_allocate_temp(ctx, instr->ssa_args.src0);
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instr->ssa_args.src1 = find_or_allocate_temp(ctx, instr->ssa_args.src1);
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instr->ssa_args.src2 = find_or_allocate_temp(ctx, instr->ssa_args.src2);
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instr->ssa_args.src3 = find_or_allocate_temp(ctx, instr->ssa_args.src3);
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instr->ssa_args.dest = find_or_allocate_temp(ctx, instr->ssa_args.dest);
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}
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}
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uint32_t nodes = ctx->num_temps;
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struct ra_graph *g = ra_alloc_interference_graph(regs, nodes);
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mir_foreach_block(ctx, block) {
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mir_foreach_instr_in_block(block, instr) {
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if (instr->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
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if (instr->dest_components == 4)
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ra_set_node_class(g, instr->ssa_args.dest, vec4_class);
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else if (instr->dest_components == 3)
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ra_set_node_class(g, instr->ssa_args.dest, vec3_class);
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else if (instr->dest_components == 2)
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ra_set_node_class(g, instr->ssa_args.dest, vec2_class);
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else
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ra_set_node_class(g, instr->ssa_args.dest, primary_class);
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}
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}
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uint32_t *live_start = malloc(nodes * sizeof(uint32_t));
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uint32_t *live_end = malloc(nodes * sizeof(uint32_t));
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memset(live_start, 0xFF, nodes * sizeof(uint32_t));
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memset(live_end, 0xFF, nodes * sizeof(uint32_t));
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uint32_t location = 0;
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mir_foreach_block(ctx, block) {
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mir_foreach_instr_in_block(block, instr) {
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if (instr->ssa_args.dest < SSA_FIXED_MINIMUM) {
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// If the destination isn't yet live before this point
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// then this is the point it becomes live since we wrote to it
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if (live_start[instr->ssa_args.dest] == ~0U) {
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live_start[instr->ssa_args.dest] = location;
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}
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}
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uint32_t sources[4] = {
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instr->ssa_args.src0,
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instr->ssa_args.src1,
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instr->ssa_args.src2,
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instr->ssa_args.src3,
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};
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for (unsigned i = 0; i < 4; ++i) {
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if (sources[i] >= SSA_FIXED_MINIMUM)
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continue;
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// If the source is no longer live after this instruction then we can end its liveness
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if (!is_live_after_instr(ctx, block, instr, sources[i])) {
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live_end[sources[i]] = location;
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}
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}
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++location;
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}
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}
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// Spin through the nodes quick and ensure they are all killed by the end of the program
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for (unsigned i = 0; i < nodes; ++i) {
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if (live_end[i] == ~0U)
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live_end[i] = location;
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}
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for (int i = 0; i < nodes; ++i) {
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for (int j = i + 1; j < nodes; ++j) {
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if (!(live_start[i] >= live_end[j] || live_start[j] >= live_end[i])) {
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ra_add_node_interference(g, i, j);
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}
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}
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}
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ra_set_select_reg_callback(g, ra_select_callback, NULL);
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if (!ra_allocate(g)) {
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assert(0);
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}
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free(live_start);
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free(live_end);
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mir_foreach_block(ctx, block) {
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mir_foreach_instr_in_block(block, instr) {
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instr->args.src0 = ra_get_phys_reg(ctx, g, instr->ssa_args.src0, nodes);
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instr->args.src1 = ra_get_phys_reg(ctx, g, instr->ssa_args.src1, nodes);
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instr->args.src2 = ra_get_phys_reg(ctx, g, instr->ssa_args.src2, nodes);
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instr->args.src3 = ra_get_phys_reg(ctx, g, instr->ssa_args.src3, nodes);
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instr->args.dest = ra_get_phys_reg(ctx, g, instr->ssa_args.dest, nodes);
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}
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}
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}
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static void
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bundle_block(compiler_context *ctx, bifrost_block *block)
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{
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}
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static void
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remove_create_vectors(compiler_context *ctx, bifrost_block *block)
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{
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mir_foreach_instr_in_block_safe(block, instr) {
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if (instr->op != op_create_vector) continue;
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uint32_t vector_ssa_sources[4] = {
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instr->ssa_args.src0,
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instr->ssa_args.src1,
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instr->ssa_args.src2,
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instr->ssa_args.src3,
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};
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|
||||
mir_foreach_instr_in_block_from_rev(block, next_instr, instr) {
|
||||
// Walk our block backwards and find the creators of this vector creation instruction
|
||||
for (unsigned i = 0; i < instr->dest_components; ++i) {
|
||||
// If this instruction is ther one that writes this register then forward it to the real register
|
||||
if (vector_ssa_sources[i] == next_instr->ssa_args.dest) {
|
||||
next_instr->ssa_args.dest = vector_ssa_sources[i];
|
||||
// Source instruction destination is a vector register of size dest_components
|
||||
// So dest + i gets the components of it
|
||||
next_instr->args.dest = instr->args.dest + i;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Remove the instruction now that we have copied over all the sources
|
||||
mir_remove_instr(instr);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
remove_extract_elements(compiler_context *ctx, bifrost_block *block)
|
||||
{
|
||||
mir_foreach_instr_in_block_safe(block, instr) {
|
||||
if (instr->op != op_extract_element) continue;
|
||||
|
||||
mir_foreach_instr_in_block_from(block, next_instr, instr) {
|
||||
// Walk our block forward to replace uses of this register with a real register
|
||||
// src0 = vector
|
||||
// src1 = index in to vector
|
||||
uint32_t vector_ssa_sources[4] = {
|
||||
next_instr->ssa_args.src0,
|
||||
next_instr->ssa_args.src1,
|
||||
next_instr->ssa_args.src2,
|
||||
next_instr->ssa_args.src3,
|
||||
};
|
||||
uint32_t *vector_sources[4] = {
|
||||
&next_instr->args.src0,
|
||||
&next_instr->args.src1,
|
||||
&next_instr->args.src2,
|
||||
&next_instr->args.src3,
|
||||
};
|
||||
|
||||
for (unsigned i = 0; i < 4; ++i) {
|
||||
if (vector_ssa_sources[i] == instr->ssa_args.dest) {
|
||||
// This source uses this vector extraction
|
||||
// Replace its usage with the real register
|
||||
// src0 is a vector register and src1 is the constant element of the vector
|
||||
*vector_sources[i] = instr->args.src0 + instr->literal_args[0];
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// Remove the instruction now that we have copied over all the sources
|
||||
mir_remove_instr(instr);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void schedule_program(compiler_context *ctx)
|
||||
{
|
||||
// XXX: we should move instructions together before RA that can feed in to each other and be scheduled in the same clause
|
||||
allocate_registers(ctx);
|
||||
|
||||
mir_foreach_block(ctx, block) {
|
||||
remove_create_vectors(ctx, block);
|
||||
remove_extract_elements(ctx, block);
|
||||
}
|
||||
|
||||
mir_foreach_block(ctx, block) {
|
||||
#ifdef BI_DEBUG
|
||||
print_mir_block(block, true);
|
||||
#endif
|
||||
|
||||
bundle_block(ctx, block);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef bifrost_ra_h
|
||||
#define bifrost_ra_h
|
||||
#include "compiler_defines.h"
|
||||
|
||||
void schedule_program(compiler_context *ctx);
|
||||
|
||||
#endif /* bifrost_ra_h */
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __compiler_defines_h__
|
||||
#define __compiler_defines_h__
|
||||
#include "bifrost.h"
|
||||
#include "bifrost_compile.h"
|
||||
#include "bifrost_ops.h"
|
||||
|
||||
struct nir_builder;
|
||||
|
||||
typedef struct ssa_args {
|
||||
uint32_t dest;
|
||||
uint32_t src0, src1, src2, src3;
|
||||
} ssa_args;
|
||||
|
||||
/**
|
||||
* @brief Singular unpacked instruction that lives outside of the clause bundle
|
||||
*/
|
||||
typedef struct bifrost_instruction {
|
||||
// Must be first
|
||||
struct list_head link;
|
||||
|
||||
/**
|
||||
* @brief Pre-RA arguments
|
||||
*/
|
||||
struct ssa_args ssa_args;
|
||||
uint32_t literal_args[4];
|
||||
uint32_t src_modifiers;
|
||||
unsigned op;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Post-RA arguments
|
||||
*/
|
||||
struct ssa_args args;
|
||||
|
||||
/**
|
||||
* @brief The number of components that the destination takes up
|
||||
*
|
||||
* This allows the RA to understand when it needs to allocate registers from different classes
|
||||
*/
|
||||
unsigned dest_components;
|
||||
|
||||
} bifrost_instruction;
|
||||
|
||||
typedef struct bifrost_clause {
|
||||
struct bifrost_header header;
|
||||
|
||||
/* List of bifrost_instructions emitted for the current clause */
|
||||
struct list_head instructions;
|
||||
|
||||
} bifrost_clause;
|
||||
|
||||
typedef struct bifrost_block {
|
||||
/* Link to next block. Must be first for mir_get_block */
|
||||
struct list_head link;
|
||||
|
||||
/* List of bifrost_instructions emitted for the current block */
|
||||
struct list_head instructions;
|
||||
|
||||
/* List of bifrost clauses to be emitted for the current block*/
|
||||
struct util_dynarray clauses;
|
||||
|
||||
/* Maximum number of successors is 2 */
|
||||
struct bifrost_block *successors[2];
|
||||
uint32_t num_successors;
|
||||
|
||||
} bifrost_block;
|
||||
|
||||
typedef struct compiler_context {
|
||||
nir_shader *nir;
|
||||
gl_shader_stage stage;
|
||||
|
||||
/* Current NIR function */
|
||||
nir_function *func;
|
||||
struct nir_builder *b;
|
||||
|
||||
/* Unordered list of bifrost_blocks */
|
||||
uint32_t block_count;
|
||||
struct list_head blocks;
|
||||
|
||||
/* The current block we are operating on */
|
||||
struct bifrost_block *current_block;
|
||||
|
||||
struct hash_table_u64 *ssa_constants;
|
||||
|
||||
/* Uniform IDs */
|
||||
struct hash_table_u64 *uniform_nir_to_bi;
|
||||
uint32_t uniform_count;
|
||||
|
||||
struct hash_table_u64 *varying_nir_to_bi;
|
||||
uint32_t varying_count;
|
||||
|
||||
struct hash_table_u64 *outputs_nir_to_bi;
|
||||
uint32_t outputs_count;
|
||||
|
||||
/* Count of instructions emitted from NIR overall, across all blocks */
|
||||
uint32_t instruction_count;
|
||||
|
||||
uint32_t mir_temp;
|
||||
|
||||
struct hash_table_u64 *hash_to_temp;
|
||||
uint32_t num_temps;
|
||||
|
||||
uint32_t max_hash;
|
||||
|
||||
} compiler_context;
|
||||
|
||||
#define mir_foreach_block(ctx, v) list_for_each_entry(struct bifrost_block, v, &ctx->blocks, link)
|
||||
#define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct bifrost_block, v, from, &ctx->blocks, link)
|
||||
|
||||
#define mir_last_block(ctx) list_last_entry(&ctx->blocks, struct bifrost_block, link)
|
||||
|
||||
#define mir_foreach_instr(ctx, v) list_for_each_entry(struct bifrost_instruction, v, &ctx->current_block->instructions, link)
|
||||
#define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct bifrost_instruction, v, &block->instructions, link)
|
||||
#define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct bifrost_instruction, v, from, &block->instructions, link)
|
||||
#define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct bifrost_instruction, v, &block->instructions, link)
|
||||
#define mir_last_instr_in_block(block) list_last_entry(&block->instructions, struct bifrost_instruction, link)
|
||||
#define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct bifrost_instruction, v, from, &block->instructions, link)
|
||||
|
||||
#define mir_next_instr(from) list_first_entry(&(from->link), struct bifrost_instruction, link)
|
||||
#define mir_remove_instr(instr) list_del(&instr->link)
|
||||
|
||||
#define mir_insert_instr_before(before, ins) list_addtail(&(mir_alloc_ins(ins))->link, &before->link)
|
||||
|
||||
#define SSA_INVALID_VALUE ~0U
|
||||
#define SSA_TEMP_SHIFT 24
|
||||
#define SSA_FIXED_REGISTER_SHIFT 25
|
||||
|
||||
#define SSA_FIXED_REGISTER(x) ((1U << SSA_FIXED_REGISTER_SHIFT) + (x))
|
||||
#define SSA_REG_FROM_FIXED(x) ((x) & ~(1U << SSA_FIXED_REGISTER_SHIFT))
|
||||
|
||||
#define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
|
||||
#define SSA_FIXED_UREG_MINIMUM SSA_FIXED_REGISTER(64)
|
||||
#define SSA_FIXED_CONST_0 SSA_FIXED_REGISTER(256 + 64)
|
||||
|
||||
#define SSA_FIXED_UREGISTER(x) (SSA_FIXED_REGISTER(x + 64))
|
||||
#define SSA_UREG_FROM_FIXED(x) (SSA_REG_FROM_FIXED(x) - 64)
|
||||
|
||||
#define SSA_TEMP_VALUE(x) ((1U << SSA_TEMP_SHIFT) + (x))
|
||||
#define SSA_TEMP_FROM_VALUE(x) (((x) & ~(1U << SSA_TEMP_SHIFT)))
|
||||
#define MIR_TEMP_MINIMUM SSA_TEMP_VALUE(0)
|
||||
|
||||
#define SRC_MOD_ABS 1
|
||||
#define SRC_MOD_NEG 2
|
||||
#define MOD_SIZE 2
|
||||
#define SOURCE_MODIFIER(src, mod) (mod << (src * MOD_SIZE))
|
||||
|
||||
struct bifrost_instruction *
|
||||
mir_alloc_ins(struct bifrost_instruction instr);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue