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pan/bi: Add src/dest fields to bifrost_instruction 

...along with some helpers to generate indices. The indexing scheme is
mostly a copypaste from Midgard, except we specifically reserve 0 as the
sentinel (midgard uses ~0 for this which has always been a pain point).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
This commit is contained in:
Alyssa Rosenzweig 2020-03-02 20:24:03 -05:00 committed by Marge Bot
parent e7dc2a7b9b
commit 230be61f20
1 changed files with 41 additions and 0 deletions
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41
src/panfrost/bifrost/compiler.h
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@ -68,9 +68,17 @@ enum bi_class {
BI_ROUND,
};
/* It can't get any worse than csel4... can it? */
#define BIR_SRC_COUNT 4
typedef struct {
struct list_head link; /* Must be first */
enum bi_class type;
/* Indices, see bir_ssa_index etc. Note zero is special cased
* to "no argument" */
unsigned dest;
unsigned src[BIR_SRC_COUNT];
} bi_instruction;
typedef struct {
@ -83,4 +91,37 @@ typedef struct {
struct list_head blocks; /* list of bi_block */
} bi_context;
/* So we can distinguish between SSA/reg/sentinel quickly */
#define BIR_NO_ARG (0)
#define BIR_IS_REG (1)
static inline unsigned
bir_ssa_index(nir_ssa_def *ssa)
{
/* Off-by-one ensures BIR_NO_ARG is skipped */
return ((ssa->index + 1) << 1) | 0;
}
static inline unsigned
bir_src_index(nir_src *src)
{
if (src->is_ssa)
return bir_ssa_index(src->ssa);
else {
assert(!src->reg.indirect);
return (src->reg.reg->index << 1) | BIR_IS_REG;
}
}
static inline unsigned
bir_dest_index(nir_dest *dst)
{
if (dst->is_ssa)
return bir_ssa_index(&dst->ssa);
else {
assert(!dst->reg.indirect);
return (dst->reg.reg->index << 1) | BIR_IS_REG;
}
}
#endif