Commit Graph

77350 Commits

Author SHA1 Message Date
Chad Versace ea20389320 anv: Add FIXME for vkResetCommandPool
vkResetCommandPool currently destroys its command buffers. The Vulkan
1.0 spec requires that it only reset them:

    Resetting a command pool recycles all of the resources from all of
    the command buffers allocated from the command pool back to the
    command pool. All command buffers that have been allocated from the
    command pool are put in the initial state.
2016-01-14 13:14:40 -08:00
Chad Versace 20fd816b6b anv: Remove duplicate func prototype
anv_private.h declared anv_cmd_buffer_begin_subpass twice.
2016-01-14 13:14:40 -08:00
Chad Versace 0415dfcfe7 anv/meta: Add FINISHME for clearing multi-layer framebuffers 2016-01-14 13:14:40 -08:00
Jason Ekstrand 32f8bcb84f i965/vec4: Use UW type for multiply into accumulator on GEN8+
BDW adds the following restriction: "When multiplying DW x DW, the dst
cannot be accumulator."
2016-01-14 12:04:25 -08:00
Jason Ekstrand 45349acad0 Merge remote-tracking branch 'mesa-public/master' into vulkan
This fixes the bitfieldextract and bitfieldinsert CTS tests
2016-01-14 11:36:27 -08:00
Ilia Mirkin e94ef885bb st/mesa: use surface format to generate mipmaps when available
This fixes the recently posted mipmap + texture views piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-14 14:28:04 -05:00
Marek Olšák dc96a18d24 radeonsi: don't miss changes to SPI_TMPRING_SIZE
I'm not sure about the consequences of this bug, but it's definitely
dangerous.

This applies to SI, CIK, VI.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-14 19:55:41 +01:00
Charmaine Lee 6303231a1d svga: add DXGenMips command support
For those formats that support hw mipmap generation, use the
DXGenMips command. Otherwise fallback to the mipmap generation utility.

Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench)

v2: make sure the texture surface was created with the render target bind flag
    set relocation flag to SVGA_RELOC_WRITE for the texture surface

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:44:25 -07:00
Charmaine Lee 78e628ae43 svga: add num-generate-mipmap HUD query
The actual increment of the num-generate-mipmap counter will be done
in a subsequent patch when hw generate mipmap is supported.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:39:53 -07:00
Charmaine Lee 3038e8984d gallium/st: add pipe_context::generate_mipmap()
This patch adds a new interface to support hardware mipmap generation.
PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify
if this new interface is supported; if not supported, the state tracker will
fallback to mipmap generation by rendering/texturing.

v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers
v3: add format to the generate_mipmap interface to allow mipmap generation
    using a format other than the resource format
v4: fix return type of trace_context_generate_mipmap()

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:39:53 -07:00
Brian Paul b1e11f4d71 st/mesa: declare struct pipe_screen in st_cb_bufferobjects.h
To silence a compiler warning.  Trivial.
2016-01-14 10:38:18 -07:00
Matt Turner b82e26a6a4 nir: Lower bitfield_extract.
The OpenGL specifications for bitfieldExtract() says:

   The result will be undefined if <offset> or <bits> is negative, or if
   the sum of <offset> and <bits> is greater than the number of bits
   used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits
of the width operand, making them not able to implement the GLSL-specified
behavior directly.

This commit adds ubfe/ibfe operations from SM5 and a lowering pass for
bitfield_extract to to handle the trivial case of <bits> = 32 as

   bitfieldExtract:
      bits > 31 ? value : bfe(value, offset, bits)

Fixes:
   ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
2016-01-14 09:28:01 -08:00
Matt Turner 15640ee77a nir: Handle <bits>=32 case in bitfield_insert lowering.
The OpenGL specifications for bitfieldInsert() says:

   The result will be undefined if <offset> or <bits> is negative, or if
   the sum of <offset> and <bits> is greater than the number of bits
   used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier SM5 bfi opcode is specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low
5 bits of the width operand, making them not able to implement the
GLSL-specified behavior directly.

This commit fixes the lowering of bitfield_insert to handle the trivial
case of <bits> = 32 as

   bitfieldInsert:
      bits > 31 ? insert : bfi(bfm(bits, offset), insert, base)

Fixes:
   ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2
   ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
2016-01-14 09:27:52 -08:00
Jason Ekstrand f46f4e4886 nir/spirv: Add initial support for Vertex/Instance index 2016-01-14 09:12:32 -08:00
Jason Ekstrand 3d0fac7aca vulkan.h: Pull in 1.0.1 header 2016-01-14 08:37:54 -08:00
Jason Ekstrand 24a6fcba77 vulkan-1.0.0: Bump the version to 1.0.0 2016-01-14 08:26:37 -08:00
Jason Ekstrand c310fb032d vulkan-1.0.0: Rework memory barriers 2016-01-14 08:09:39 -08:00
Brian Paul 6470435190 st/mesa: add check for color logicop in blit_copy_pixels()
We check that a bunch of raster operations are disabled in
blit_copy_pixels().  We also need to check that color logicop is
disabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:08:21 -07:00
Jason Ekstrand b14a78cfb8 vulkan-1.0.0: No-op WSI changes 2016-01-14 08:02:44 -08:00
Jason Ekstrand 6d3322d0e5 vulkan-1.0.0: Make extents unsigned 2016-01-14 08:00:18 -08:00
Jason Ekstrand b57c72d964 vulkan-1.0.0: Rework blits to use four offsets 2016-01-14 07:59:37 -08:00
Jason Ekstrand f6cae99294 vulkan-1.0.0: Split out command buffer inheritance info 2016-01-14 07:45:15 -08:00
Jason Ekstrand f99f847412 vulkan-1.0.0: Re-order some structs in the header 2016-01-14 07:43:05 -08:00
Jason Ekstrand aab9517f3d vulkan-1.0.0: Misc. field and argument renames 2016-01-14 07:41:45 -08:00
Jason Ekstrand d877095e66 vulkan-1.0.0: Get rid of MIPMAP_MODE_BASE 2016-01-14 07:32:16 -08:00
Jason Ekstrand 7b81637762 vulkan-1.0.0: Convert pPreserveAttachments to a uint32_t 2016-01-14 07:30:46 -08:00
Jason Ekstrand 802f00219a anv/device: Update features and limits 2016-01-14 07:30:46 -08:00
Jason Ekstrand 08735ba91c anv/cmd_buffer: Fix setting of viewport/scissor count 2016-01-14 07:30:46 -08:00
Jason Ekstrand ed4fe3e9ba anv/state: Respect SamplerCreateInfo.anisotropyEnable 2016-01-14 07:30:46 -08:00
Jason Ekstrand 8a81d136f8 anv/image: Fill out VkSubresourceLayout.arrayPitch 2016-01-14 07:30:46 -08:00
BogDan Vatra 102c74277f WIP: Partially upgrade to vulkan v0.221.0
TODO, make use of:
- VkPhysicalDeviceFeatures.drawIndirectFirstInstance,
- VkPhysicalDeviceFeatures.inheritedQueries
- VkPhysicalDeviceLimits.timestampComputeAndGraphics
- VkSubmitInfo.pWaitDstStageMask
- VkSubresourceLayout.arrayPitch
- VkSamplerCreateInfo.anisotropyEnable
2016-01-14 07:30:46 -08:00
Nicolai Hähnle e976860638 gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:24 -05:00
Nicolai Hähnle 321140d563 gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:04 -05:00
Nicolai Hähnle 08c71740ad gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
This accomodates a streaming pattern where the discard flag is set when the
application wraps back to the beginning of the buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:40:00 -05:00
Nicolai Hähnle 70e66c57bb st/mesa: implement Driver.InvalidateBufferSubData
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:39:57 -05:00
Nicolai Hähnle 9e2240e892 st/mesa: use pipe->invalidate_resource instead of buffer re-allocation
Drivers are expected to avoid unnecessary work when possible in this code
path.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:39:53 -05:00
Nicolai Hähnle 654670b404 gallium: add PIPE_CAP_INVALIDATE_BUFFER
It makes sense to re-use pipe->invalidate_resource for the purpose of
glInvalidateBufferData, but this function is already implemented in vc4
where it doesn't have the expected behavior. So add a capability flag
to indicate that the driver supports the expected behavior.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:39:38 -05:00
Nicolai Hähnle 6f4ae81005 mesa: add Driver.InvalidateBufferSubData
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-14 09:39:30 -05:00
Nicolai Hähnle 53c77494aa mesa: fix the checks in _mesa_InvalidateBuffer(Sub)Data
Change the check to be in line with what the quoted spec fragment says.

I have sent out a piglit test for this as well.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-01-14 09:39:22 -05:00
Nicolai Hähnle cbcdef7b40 winsys/radeon: fix warnings about incompatible pointer types
Some confusion between pb_buffer and radeon_bo as well as between
radeon_drm_winsys and radeon_winsys.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:33:58 -05:00
Neil Roberts 06b526de05 texobj: Check completeness with InternalFormat rather than Mesa format
The internal Mesa format used for a texture might not match the one
requested in the internalFormat when the texture was created, for
example if the driver is internally remapping RGB textures to RGBA.
Otherwise it can cause false positives for completeness if one mipmap
image is created as RGBA and the other as RGB because they would both
have an RGBA Mesa format. If we check the InternalFormat instead then
we are directly checking the API usage which I think better matches
the intention of the check.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93700
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-01-14 12:18:24 +00:00
Jordan Justen 8ce2b0e140 nir/spirv: Add support for ArrayLength op
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-13 23:34:45 -08:00
Jason Ekstrand 4507d8a57a nir/spirv/alu: Properly implement mod/rem 2016-01-13 16:53:02 -08:00
Jason Ekstrand 7d5ae2d34b i965: Implement nir_op_irem and nir_op_srem 2016-01-13 16:53:02 -08:00
Ben Widawsky f4ab7340ca i965: Remove unused hw_must_use_separate_stencil
I spotted this while looking for what needs updating in future platforms.

I'm too lazy to go through the git logs, but it was probably missed by Jason
when all the brw refactoring happened.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-01-13 16:41:04 -08:00
Matt Turner 138a7dc826 i965: Drop extra newline from shader compile messages.
Ilia changed shader-db's run.c to not expect messages to contain a
newline in shader-db commit 51bbc8035.
2016-01-13 16:19:18 -08:00
Jason Ekstrand cac99fffdb nir: Add more modulus and remainder opcodes
SPIR-V makes a distinction between "modulus" and "remainder" for both
floating-point and signed integer variants.  The difference is primarily
one of which source they take their sign from.  The "remainder" opcode for
integers is equivalent to the C/C++ "%" operation while the "modulus"
opcode is more mathematically correct (at least for an unsigned divisor).
This commit adds corresponding opcodes to NIR.
2016-01-13 15:18:36 -08:00
Jason Ekstrand 0079523a0d nir/spirv: Add support for OpSpecConstantOp 2016-01-13 15:18:36 -08:00
Jason Ekstrand 8c408b9b81 nir/spirv/alu: Factor out the opcode table 2016-01-13 15:18:36 -08:00
Jason Ekstrand 9b7e08118b anv/pipeline: Pass through specialization constants 2016-01-13 15:18:36 -08:00