Commit Graph

72964 Commits

Author SHA1 Message Date
Marta Lofstedt 6c3de8996f mesa/es3.1 : Align OpenGL ES 3.1 glBindVertexBuffer error handling with OpenGL Core
According to OpenGL ES 3.1 specification 10.3.1:
"An INVALID_OPERATION error is generated if buffer is not zero
or a name returned from a previous call to GenBuffers,
or if such a name has since been deleted with DeleteBuffers."
This error check was previously limited to OpenGL Core.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
2015-09-22 12:21:59 +02:00
Tapani Pälli 7f8815bcb9 i965: fix textureGrad for cubemaps
Fixes bugs exposed by commit
2b1cdb0edd in:
   ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_frag

No regressions observed in deqp, CTS or Piglit.

v2: address review feedback from Iago Toral:
   - move rho calculation to else branch
   - optimize dx and dy calculation
   - fix documentation inconsistensies

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91114
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-09-22 08:14:20 +03:00
Kenneth Graunke 5cede90f62 nir: Report progress from nir_normalize_cubemap_coords().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:54:34 -07:00
Kenneth Graunke d7ffd90ecb nir: Add braces around multi-line loop.
This was correct but not our usual style.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:47:01 -07:00
Kenneth Graunke 0a1adaf11d nir: Report progress from nir_lower_system_values().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:47:00 -07:00
Kenneth Graunke dc18b9357b nir: Report progress from nir_split_var_copies().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:46:59 -07:00
Kenneth Graunke cfae0f8a3a nir: Report progress from nir_lower_locals_to_regs().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:46:57 -07:00
Kenneth Graunke 1adde5b87e nir: Report progress from nir_remove_dead_variables().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:46:55 -07:00
Jason Ekstrand 9f5e7ae9d8 nir: Report progress from lower_vec_to_movs().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:46:54 -07:00
Kenneth Graunke 967a5ddb88 nir: Report progress from nir_lower_globals_vars_to_local().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-21 13:46:45 -07:00
Jason Ekstrand 60befc6347 i965: Clean up GLSL compiler option setup
The only functional change here is that we now set EmitNoIndirectOutput and
EmitNoIndirectTemp for compute shaders.  Compute shaders don't have outputs
per-se and we should have been setting EmitNoIndirectTemp all along.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-09-21 13:26:52 -07:00
Jeremy Huddleston 6dfc5e28f7 configure.ac: Add support to enable read-only text segment on x86.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/240956
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-09-21 12:47:09 -07:00
Ben Widawsky c1e38ad370 i965/skl: Use larger URB size where available.
All SKL SKUs except the lowest one which has half the L3 size actually have 384K
of URB per slice.

For once, I can explain how this mistake was made and how it was missed in
review...  Historically when we enable a platform and put the production sizes,
you can simply look at the "smallest" SKU and see what its URB size is (and we
assumed it was the 1 slice variant). Since on newer platforms the URB sizes are
scaled automatically by HW, this was sufficient. On SKL, this is a bit different
as the lowest SKU actually has half of the L3 fused off. GT2 is the 1 slice (not
GT1) variant and it has 384K.

There are no Jenkins tests fixed (or regressions) and we don't expect any fixes
here because you can always run with less URB size.

Thanks to Sarah for bringing this to my attention.

Cc: Sarah Sharp <sarah.a.sharp@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-09-21 11:27:08 -07:00
Jason Ekstrand 46362db4a6 nir/builder: Don't use designated initializers
Designated initializers are not allowed in C++ (not even C++11).  Since
nir_lower_samplers is now using nir_builder, and nir_lower_samplers is in
C++, this breaks the build on some compilers.  Aparently, GCC 5 allows it
in some limited extent because mesa still builds on my system without this
patch.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92052
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 10:41:43 -07:00
Jason Ekstrand d513388c8a nir: Move system value -> intrinsic mapping into nir.c
This way they're right next to the map going the other direction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 09:49:40 -07:00
Emil Velikov de7ffdb383 nir: rename nir_lower_samplers.c{pp,}
With the only C++ function having its own wrapper we can 'demote' this
file to a normal C one. This allows us to get rid of extern C { #include
<foo.h> } 'hacks'. Plus some of the headers may use C99 initializers,
which are not supported by the ISO standard.

This may cause build issue on incremental builds. If so run the
following:

sed -i -e 's|samplers\.cpp|samplers.c|' src/glsl/nir/.deps/nir_lower_samplers.Plo

Fixes: ef8eebc6ad5(nir: support indirect indexing samplers in struct arrays)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: Gottfried Haider <gottfried.haider@gmail.com>
Tested-by: Gottfried Haider <gottfried.haider@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-09-21 17:02:06 +01:00
Emil Velikov d130cda453 nir: add C wrapper around glsl_type::record_location_offset
This will allow us to convert nir_lower_sampler.cpp to C.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Gottfried Haider <gottfried.haider@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-09-21 17:01:56 +01:00
Emil Velikov bdb1faf44e nir: move stdio.h inclusion before extern C
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Gottfried Haider <gottfried.haider@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-09-21 17:01:32 +01:00
Kenneth Graunke c1070550c2 i965: Fix MRF register number assertions for compr4.
compr4 is represented by setting the high bit on the MRF number.
We need to mask it out before sanity checking the register number.

Fixes ~8000 assert fails on Ironlake and G45.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92066
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 07:45:14 -07:00
Ilia Mirkin 72ebd532a1 radeonsi: implement TXQS support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Fredrik Bruhn <f@unibap.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-09-21 08:31:29 -04:00
Ilia Mirkin 7d5162bdc0 radeonsi: load fmask ptr relative to the resources array
res_ptr already contains the resource values. fmask_ptr needs to be
looked up relative to the start of the resource params.

Note that this only affects indirect loads of MS sampler arrays.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
2015-09-21 08:30:51 -04:00
Iago Toral Quiroga 5d23ce2f15 i965/vec4: Use MRF registers 21-23 for spilling in gen6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 12:48:05 +02:00
Iago Toral Quiroga 6789a32075 i965/fs: Use MRF registers 21-23 for spilling in gen6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 12:47:56 +02:00
Iago Toral Quiroga f50645d05c i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generation
There are some bug reports about shaders failing to compile in gen6
because MRF 14 is used when we need to spill. For example:
https://bugs.freedesktop.org/show_bug.cgi?id=86469
https://bugs.freedesktop.org/show_bug.cgi?id=90631

Discussion in bugzilla pointed to the fact that gen6 might actually have
24 MRF registers available instead of 16, so we could use other MRF
registers and avoid these conflicts (we still need to investigate why
some shaders need up to MRF 14 anyway, since this is not expected).

Notice that the hardware docs are not clear about this fact:

SNB PRM Vol4 Part2's "Table 5-4. MRF Registers Available in Device
Hardware" says "Number per Thread" - "24 registers"

However, SNB PRM Vol4 Part1, 1.6.1 Message Register File (MRF) says:

"Normal threads should construct their messages in m1..m15. (...)
Regardless of actual hardware implementation, the thread should
not assume th at MRF addresses above m15 wrap to legal MRF registers."

Therefore experimentation was necessary to evaluate if we had these extra
MRF registers available or not. This was tested in gen6 using MRF
registers 21..23 for spilling and doing a full piglit run (all.py) forcing
spilling of everything on the FS backend. It was also tested by doing
spilling of everything on both the FS and the VS backends with a piglit run
of shader.py. In both cases no regressions were observed. In fact, many of
these tests where helped in the cases where we forced spilling, since that
triggered the same underlying problem described in the bug reports. Here are
some results using INTEL_DEBUG=spill_fs,spill_vec4 for a shader.py run on
gen6 hardware:

Using MRFs 13..15 for spilling:
crash: 2, fail: 113, pass: 6621, skip: 5461

Using MRFs 21..23 for spilling:
crash: 2, fail: 12, pass: 6722, skip: 5461

This patch sets the ground for later patches to implement spilling
using MRF registers 21..23 in gen6.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 12:47:45 +02:00
Iago Toral Quiroga 0858610836 i965: Move MRF register asserts out of brw_reg.h
In a later patch we will make BRW_MAX_MRF return a different value depending
on the hardware generation, but it is inconvenient to add a gen parameter
to the brw_reg functions only for the assertions, so move these to places where
we have the hardware generation available.

Ken suggested to add the asserts to brw_set_src0 and brw_set_dest since that
would make sure that we catch all uses of MRF registers, even those coming
from modules that generate native code directly, like blorp. Unfortunately,
this is very late in the process which can make things harder to debug, so add
asserts to the generator as well.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 12:47:35 +02:00
Iago Toral Quiroga d48ac93066 i965: Maximum allowed size of SEND messages is 15 (4 bits)
Until now we only used MRFs 1..15 for regular SEND messages, so the
message length could not possibly exceed the maximum size. Soon we'll
allow to use MRF registers 1..23 in gen6, so we need to be careful
not to build messages that can go beyond the limit. That could occur,
specifically, when building URB write messages, which we may need to
split in chunks due to their size. Previously we would simply go and
create a new message when we reached MRF 13 (since 13..15 were
reserved for spilling), now we also want to check the size of the
message explicitly.

Besides adding that condition to split URB write messages properly,
this patch also adds asserts in the generator. Notice that
brw_inst_set_mlen already asserts for this, but asserting in the
generators is easy and can make debugging easier in some cases.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-21 12:47:03 +02:00
Rob Clark b65f91dd32 nir/print: fix coverity error
Not something actually hit in real life (now state is never non-null,
but only case state->syms is null is if nir_print_instr() path).  But it
was something I overlooked the first time, so might as well fix it.

    *** CID 1324642:  Null pointer dereferences  (REVERSE_INULL)
    /src/glsl/nir/nir_print.c: 299 in print_var_decl()
    293
    294           fprintf(fp, " (%s, %u)", loc, var->data.driver_location);
    295        }
    296
    297        fprintf(fp, "\n");
    298
    >>>     CID 1324642:  Null pointer dereferences  (REVERSE_INULL)
    >>>     Null-checking "state" suggests that it may be null, but it has already been dereferenced on all paths leading to the check.
    299        if (state) {
    300           _mesa_set_add(state->syms, name);
    301           _mesa_hash_table_insert(state->ht, var, name);
    302        }
    303     }
    304

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-20 14:04:06 -04:00
Eduardo Lima Mitev 6ba291db4b i965/vec4/nir: Remove all "this->" snippets
For consistency, either we have all class members dereferenced, or none.
In this case, very few are so lets get rid of them all.

Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-20 17:11:49 +02:00
Marcin Ślusarz 8f6fd57db2 dri/common: fix gbm-symbols-check regression
Broken by commit c228514c72
"dri/common: use sysconfdir when looking for drirc".

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92054
Signed-off-by: Marcin Ślusarz <marcin.slusarz@gmail.com>
2015-09-20 13:44:07 +02:00
Emil Velikov 1e01db0fa9 docs: add news item and link release notes for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-09-20 11:59:24 +01:00
Emil Velikov 278a32374c docs: add sha256 checksums for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 02387926addc62198c9b684f4f51f7cbe06b3e25)
2015-09-20 11:58:04 +01:00
Emil Velikov 72d407da10 docs: add release notes for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 91c6302734574e91424a7ccb52b6368b712366cc)
2015-09-20 11:58:03 +01:00
Nanley Chery 99b1f4751f mesa/teximage: reuse compressed format utility functions for base_format
Reuse utility functions instead of reimplementing the same logic.

* _mesa_is_compressed_format() performs the required checking to
  determine format support in the current context.
* _mesa_gl_compressed_format_base_format() returns the base format.

As a side effect, we now check that we're in a desktop context when
determining support for the FXT1 and RGTC formats. This is in agreement
with our extension table and the glext headers.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-19 13:27:15 -07:00
Nanley Chery db2777091d mesa/texcompress: add compressed formats to base format utility function
Add S3TC and PALETTE formats.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-19 13:27:10 -07:00
Nanley Chery 29835fe19e mesa/glformats: refactor compressed format support function
Instead of case statements, use _mesa_get_format_layout() to
determine if a GL format is part of a family of compressed formats.

v2. restrict LATC formats to API_OPENGL_COMPAT (Ilia).
    rename the variable mFormat to m_format.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-19 13:26:55 -07:00
Nanley Chery 31a5135cd7 mesa/formats: add MESA_LAYOUT_LATC
This enables us to predicate statments on a compressed format being
a type of LATC format. Also, remove the comment that lists the enum
(it was getting a tad long).

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-19 13:25:59 -07:00
Marcin Ślusarz c228514c72 dri/common: use sysconfdir when looking for drirc
Useful when locally installed mesa has more quirks than the system one.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-09-19 19:17:34 +02:00
Rob Clark 9ffc1049ca freedreno/ir3: use nir two-sided-color lowering
With this, we completely switch over to nir lowering passes instead of
tgsi_lowering.  So one step closer to supporting direct glsl or spirv to
nir support for freedreno a3xx/a4xx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-18 21:07:50 -04:00
Rob Clark e13ed3ffb4 nir: add two-sided-color lowering pass
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-09-18 21:07:50 -04:00
Rob Clark e4dfcdcbec nir/build: add nir_vec() helper
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-09-18 21:07:50 -04:00
Rob Clark c71cb670ba freedreno/ir3: lower txp/clamp in NIR
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-18 21:07:50 -04:00
Rob Clark 3745c38425 nir/lower_tex: add support to clamp texture coords
Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the
shader to emulate GL_CLAMP.  This is added to lower_tex_proj since, in
the case of projected coords, the clamping needs to happen *after*
projection.

v2: comments/suggestions from Ilia and Eric, use txs to get texture size
and clamp RECT textures to their dimensions rather than [0.0, 1.0] to
avoid having to lower RECT textures to 2D.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-18 21:07:49 -04:00
Rob Clark 1ce8060c25 nir/lower_tex: support for lowering RECT textures
v2: comments/suggestions from Ilia and Eric, split out get_texture_size()
helper so we can use it in the next commit for clamping RECT textures.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-18 21:07:49 -04:00
Rob Clark faf5f174dd nir/lower_tex: support projector lowering per sampler type
Some hardware, such as adreno a3xx, supports txp on some but not all
sampler types.  In this case we want more fine grained control over
which texture projectors get lowered.

v2: split out nir_lower_tex_options struct to make it easier to
add the additional parameters coming in the following patches

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-18 21:07:49 -04:00
Rob Clark f83ba7bc41 nir/lower_tex: split out project_src() helper
Split this out to reduce noise in later patches.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-18 21:07:49 -04:00
Rob Clark d9b9ff76f1 nir: rename nir_lower_tex_projector
Since the following patches will add additional tex-lowering related
functionality, which doesn't make sense to split out into a separate
pass (as they would require duplication of the projector lowering
logic), let's give this pass a more generic name.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-18 21:07:49 -04:00
Alejandro Piñeiro 06d31dceae i965/vec4: Change types as needed to propagate source modifiers using current instruction
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around.  So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
generate.

This commit adds support for copy propagation using current instruction
as reference.

Equivalent to commit 472ef9 but for vec4.

v2: include check for saturate, as Jason Ekstrand suggested
v3: check that the dst.type and the src type are the same, in order to
    solve (among others) the following deqp regression with v2:
    dEQP-GLES3.functional.shaders.operator.unary_operator.minus.lowp_uint_vertex

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-19 00:31:25 +02:00
Iago Toral Quiroga f7ca52dd6d i965/fs: Fix comparison between signed and unsigned integer expressions
brw_fs_visitor.cpp: In member function 'void fs_visitor::emit_urb_writes()':
brw_fs_visitor.cpp:977:58: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-18 13:37:25 +02:00
Tapani Pälli afa1efdc85 mesa: fix errors when reading depth with glReadPixels
OpenGL ES 3.0 spec 3.7.2 "Transfer of Pixel Rectangles" specifies
DEPTH_COMPONENT, UNSIGNED_INT as a valid couple, validation for
internal format is checked by is_float_depth().

Fix regression caused by 81d2fd91a9 in:
   ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels

Test uses GL_DEPTH_COMPONENT, UNSIGNED_INT only when GL_NV_read_depth
extension is present.

v2: change check in _mesa_error_check_format_and_type to be explicit
    for ES 2.0+, desktop OpenGL does not allow this behaviour + uses
    this function for both glReadPixels and glDrawPixels validation.
    (No Piglit regressions seen with v2.)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> [v1]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92009
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-09-18 07:41:47 +03:00
Rob Clark 2e4ab489b5 nir/builder: fix c++11 compiler warning
Fixes:

   In file included from nir/nir_lower_samplers.cpp:27:0:
   nir/nir_builder.h: In function 'nir_ssa_def* nir_channel(nir_builder*, nir_ssa_def*, int)':
   nir/nir_builder.h:222:37: warning: narrowing conversion of 'c' from 'int' to 'unsigned int' inside { } is ill-formed in C++11 [-Wnarrowing]
       unsigned swizzle[4] = {c, c, c, c};

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-17 21:08:25 -04:00