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393 Commits

Author SHA1 Message Date
Marek Olšák e395475096 radeonsi: remove function si_init_atom 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák 639b673fc3 radeonsi: don't use an indirect table for state atoms 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák 9054799b39 radeonsi: rename r600_atom -> si_atom 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák 60299e9abe radeonsi: don't emit partial flushes for internal CS flushes only 
Tested-by: Benedikt Schemmer <ben@besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-16 16:58:10 -04:00
Marek Olšák 6a93441295 radeonsi: remove r600_common_context 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 5777488406 radeonsi: move r600_cs.h contents into si_pipe.h, si_build_pm4.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 72e9e98076 radeonsi: move and rename R600_ERR out of r600_pipe_common.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 5f1cddde78 radeonsi: move definitions out of r600_pipe_common.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák c424f86180 radeonsi: use si_context instead of pipe_context in parameters pt1 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 4c5efc40f4 radeonsi: update copyrights 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 95bc30275b radeonsi: switch radeon_add_to_buffer_list parameter to si_context 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 2b70dd8c8a radeonsi: flatten / remove struct r600_ring 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 17e8f1608e radeonsi: call CS flush functions directly whenever possible 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák 0669dca9c0 radeonsi: skip DCC render feedback checking if color writes are disabled 2018-04-05 15:34:58 -04:00
Marek Olšák 2be6143032 radeonsi: implement GL_KHR_blend_equation_advanced 
MSAA is supported using sample shading. Layered rendering and all texture
targets are also supported.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-04-02 13:55:25 -04:00
Marek Olšák 9b7db12815 radeonsi: remove chip_class parameter from si_lower_nir 
We can get it from si_screen.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-08 14:58:16 -05:00
Marek Olšák 2e30268877 radeonsi: mask out high VM address bits in registers where needed 2018-03-07 13:55:35 -05:00
Timothy Arceri 70190a6567 radeonsi/nir: call ac_lower_indirect_derefs() 
Fixes piglit tests:
tests/spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd.shader_test
tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-03-05 14:09:23 +11:00
Timothy Arceri 561503e3bd radeonsi: add chip class to compiler_ctx_state 
This will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-03-05 14:09:23 +11:00
Marek Olšák 8799eaed99 radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers 
The effect of the last 13 commits on user SGPR counts:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-26 12:01:19 +01:00
Marek Olšák 3fa7a59d69 radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input 
so that it can be removed and replaced with inline VBO descriptors,
and the pointer can be packed in unused bits of VBO descriptors.
This also removes the pointer from merged TES-GS where it's useless.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-26 12:01:08 +01:00
Marek Olšák 2d03c4cac8 radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRs 
TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address
aligned to 512KB. Hey, it's a 13-bit pointer!

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-24 23:08:29 +01:00
Marek Olšák fca7dee9c6 radeonsi: put both tessellation rings into 1 buffer 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-24 23:08:28 +01:00
Marek Olšák d2963d8b5f radeonsi: move tessellation ring info into si_screen 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-24 23:08:28 +01:00
Timothy Arceri 691c320de0 radeonsi: add nir shader cache support 
In future we might want to try avoid calling nir_serialize() but
this works for now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-02-20 13:15:02 +11:00
Timothy Arceri 2b431808ab radeonsi: rename variables tgsi_binary -> ir_binary 
This better represents that the ir could be either tgsi or nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-02-20 13:15:02 +11:00
Marek Olšák fdf01d0244 radeonsi: remove DBG_PRECOMPILE 
it's useless and shader-db stats only report the main shader part.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-01-31 03:21:20 +01:00
Marek Olšák 148b48646b radeonsi: print shader-db stats for main parts, not final binaries 
This is needed to get shader-db stats for LS,HS,ES,GS stages on gfx9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-01-31 03:21:20 +01:00
Timothy Arceri 452586b56a radeonsi: add dummy implementation of si_nir_scan_tess_ctrl() 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-01-05 11:58:55 +11:00
Józef Kucia f222cf3c6d radeonsi: fix alpha-to-coverage if color writes are disabled 
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-01-04 01:58:33 +01:00
Samuel Pitoiset 79b34d0832 amd/common: add ac_vgt_gs_mode() helper 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2017-12-18 11:50:50 +01:00
Samuel Pitoiset 55f8431c76 amd/common: add ac_get_cb_shader_mask() helper 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2017-12-18 11:50:48 +01:00
Samuel Pitoiset 45872a0a6d radeonsi: make use of ac_get_spi_shader_z_format() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2017-12-14 22:23:25 +01:00
Marek Olšák 2c5f2936af r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_* 
and handle PIPE_FLUSH_HINT_FINISH in r300.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-11-29 18:21:30 +01:00
Marek Olšák 950221f923 radeonsi: remove r600_common_screen 
Most files in gallium/radeon now include si_pipe.h.

chip_class and family are now here:
    sscreen->info.family
    sscreen->info.chip_class

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-11-29 18:21:30 +01:00
Marek Olšák 2208b760f3 radeonsi: move shader debug helpers out of r600_pipe_common.c 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-11-29 18:21:30 +01:00
Marek Olšák c63e225bff radeonsi: remove some definitions and helpers from r600_pipe_common.h 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-11-29 18:21:30 +01:00
Nicolai Hähnle f76a6cb337 radeonsi: always use async compiles when creating shader/compute states 
With Gallium threaded contexts, creating shader/compute states is
effectively a screen operation, so we should not use context state.

In particular, this allows us to avoid using the context's LLVM
TargetMachine.

This isn't an issue yet because u_threaded_context filters out non-async
debug callbacks, and we disable threaded contexts for debug contexts.
However, we may want to change that in the future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-11-09 11:53:20 +01:00
Nicolai Hähnle dd7c273e87 radeonsi: move pipe debug callback to si_context 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-11-09 11:53:19 +01:00
Nicolai Hähnle 0f54ee6072 radeonsi: reduce the scope of sel->mutex in si_shader_select_with_key 
We only need the lock to guard changes in the variant linked list. The
actual compilation can happen outside the lock, since we use the ready
fence as a guard.

v2: fix double-unlock

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-11-09 11:37:51 +01:00
Nicolai Hähnle 4f493c79ee radeonsi: use ready fences on all shaders, not just optimized ones 
There's a race condition between si_shader_select_with_key and
si_bind_XX_shader:

  Thread 1                         Thread 2
  --------                         --------
  si_shader_select_with_key
    begin compiling the first
    variant
    (guarded by sel->mutex)
                                   si_bind_XX_shader
                                     select first_variant by default
                                     as state->current
                                   si_shader_select_with_key
                                     match state->current and early-out

Since thread 2 never takes sel->mutex, it may go on rendering without a
PM4 for that shader, for example.

The solution taken by this patch is to broaden the scope of
shader->optimized_ready to a fence shader->ready that applies to
all shaders. This does not hurt the fast path (if anything it makes
it faster, because we don't explicitly check is_optimized).

It will also allow reducing the scope of sel->mutex locks, but this is
deferred to a later commit for better bisectability.

Fixes dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.bufferdata_render

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-11-09 11:37:51 +01:00
Marek Olšák 529cdce799 radeonsi: remove 'Authors:' comments 
It's inaccurate. Instead, see the copyright and use "git log" and
"git blame" to know the authorship.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-11-02 18:19:03 +01:00
Marek Olšák da0083f123 radeonsi: use postponed KILL only when derivatives are used 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-24 14:56:34 +02:00
Marek Olšák 65f2e33500 radeonsi: import r600_streamout from drivers/radeon 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-09 16:26:55 +02:00
Marek Olšák 3784ce9782 radeonsi: enumerize DBG flags 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-09 16:20:16 +02:00
Marek Olšák 5a47abb63e radeonsi: don't change viewport for blits, use window-space positions 
The viewport state was an identity anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-07 18:26:35 +02:00
Marek Olšák 13b6c1c031 radeonsi: minor cleanup of si_update_vs_writes_viewport_index 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-07 18:26:35 +02:00
Marek Olšák 69ccb9dae7 radeonsi: use new VS blit shaders (VS inputs in SGPRs) 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-07 18:26:35 +02:00
Marek Olšák 6a8401a94e radeonsi: add VS blit shader creation 
no users yet

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-10-07 18:26:35 +02:00
Nicolai Hähnle 12f3155e28 radeonsi: simplify the signature of si_update_vs_writes_viewport_index 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2017-10-02 15:07:45 +02:00