radeonsi: use new VS blit shaders (VS inputs in SGPRs)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -95,6 +95,12 @@ static void si_blitter_end(struct pipe_context *ctx)
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struct si_context *sctx = (struct si_context *)ctx;
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sctx->b.render_cond_force_off = false;
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/* Restore shader pointers because the VS blit shader changed all
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* non-global VS user SGPRs. */
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sctx->shader_pointers_dirty |= SI_VS_SHADER_POINTER_MASK;
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sctx->vertex_buffer_pointer_dirty = true;
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si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
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}
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static unsigned u_max_sample(struct pipe_resource *r)
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@ -402,6 +402,8 @@ struct si_context {
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struct r600_resource *border_color_buffer;
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union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
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unsigned border_color_count;
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unsigned num_vs_blit_sgprs;
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uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
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/* Vertex and index buffers. */
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bool vertex_buffers_dirty;
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@ -247,6 +247,11 @@ enum {
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#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
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SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
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#define SI_VS_SHADER_POINTER_MASK \
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u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
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PIPE_SHADER_VERTEX * SI_NUM_SHADER_DESCS, \
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SI_NUM_SHADER_DESCS)
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/* This represents descriptors in memory, such as buffer resources,
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* image resources, and sampler states.
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*/
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@ -563,6 +563,12 @@ static void si_emit_vs_state(struct si_context *sctx,
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sctx->current_vs_state &= C_VS_STATE_INDEXED;
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sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
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if (sctx->num_vs_blit_sgprs) {
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/* Re-emit the state after we leave u_blitter. */
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sctx->last_vs_state = ~0;
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return;
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}
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if (sctx->current_vs_state != sctx->last_vs_state) {
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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@ -795,11 +801,20 @@ static void si_emit_draw_packets(struct si_context *sctx,
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/* Base vertex and start instance. */
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base_vertex = index_size ? info->index_bias : info->start;
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if (base_vertex != sctx->last_base_vertex ||
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sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
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info->start_instance != sctx->last_start_instance ||
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info->drawid != sctx->last_drawid ||
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sh_base_reg != sctx->last_sh_base_reg) {
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if (sctx->num_vs_blit_sgprs) {
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/* Re-emit draw constants after we leave u_blitter. */
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si_invalidate_draw_sh_constants(sctx);
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/* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
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radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
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sctx->num_vs_blit_sgprs);
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radeon_emit_array(cs, sctx->vs_blit_sh_data,
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sctx->num_vs_blit_sgprs);
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} else if (base_vertex != sctx->last_base_vertex ||
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sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
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info->start_instance != sctx->last_start_instance ||
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info->drawid != sctx->last_drawid ||
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sh_base_reg != sctx->last_sh_base_reg) {
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radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
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radeon_emit(cs, base_vertex);
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radeon_emit(cs, info->start_instance);
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@ -1501,9 +1516,6 @@ void si_draw_rectangle(struct blitter_context *blitter,
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struct pipe_context *pipe = util_blitter_get_pipe(blitter);
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struct si_context *sctx = (struct si_context*)pipe;
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struct pipe_viewport_state viewport;
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struct pipe_resource *buf = NULL;
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unsigned offset = 0;
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float *vb;
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/* setup viewport */
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viewport.scale[0] = 1.0f;
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@ -1514,70 +1526,38 @@ void si_draw_rectangle(struct blitter_context *blitter,
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viewport.translate[2] = 0.0f;
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pipe->set_viewport_states(pipe, 0, 1, &viewport);
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/* Upload vertices. The hw rectangle has only 3 vertices,
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* The 4th one is derived from the first 3.
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* The vertex specification should match u_blitter's vertex element state. */
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u_upload_alloc(pipe->stream_uploader, 0, sizeof(float) * 24,
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sctx->screen->b.info.tcc_cache_line_size,
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&offset, &buf, (void**)&vb);
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if (!buf)
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return;
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vb[0] = x1;
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vb[1] = y1;
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vb[2] = depth;
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vb[3] = 1;
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vb[8] = x1;
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vb[9] = y2;
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vb[10] = depth;
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vb[11] = 1;
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vb[16] = x2;
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vb[17] = y1;
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vb[18] = depth;
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vb[19] = 1;
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/* Pack position coordinates as signed int16. */
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sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
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((uint32_t)(y1 & 0xffff) << 16);
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sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
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((uint32_t)(y2 & 0xffff) << 16);
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sctx->vs_blit_sh_data[2] = fui(depth);
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switch (type) {
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case UTIL_BLITTER_ATTRIB_COLOR:
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memcpy(vb+4, attrib->color, sizeof(float)*4);
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memcpy(vb+12, attrib->color, sizeof(float)*4);
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memcpy(vb+20, attrib->color, sizeof(float)*4);
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memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
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sizeof(float)*4);
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break;
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
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vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
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vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
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/* fall through */
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vb[4] = attrib->texcoord.x1;
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vb[5] = attrib->texcoord.y1;
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vb[12] = attrib->texcoord.x1;
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vb[13] = attrib->texcoord.y2;
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vb[20] = attrib->texcoord.x2;
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vb[21] = attrib->texcoord.y1;
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
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memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
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sizeof(attrib->texcoord));
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break;
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default:; /* Nothing to do. */
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case UTIL_BLITTER_ATTRIB_NONE:;
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}
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/* draw */
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struct pipe_vertex_buffer vbuffer = {};
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vbuffer.buffer.resource = buf;
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vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
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vbuffer.buffer_offset = offset;
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pipe->set_vertex_buffers(pipe, blitter->vb_slot, 1, &vbuffer);
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pipe->bind_vs_state(pipe, get_vs(blitter));
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if (sctx->vertex_elements != vertex_elements_cso)
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pipe->bind_vertex_elements_state(pipe, vertex_elements_cso);
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pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
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struct pipe_draw_info info = {};
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info.mode = R600_PRIM_RECTANGLE_LIST;
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info.count = 3;
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info.instance_count = num_instances;
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/* Don't set per-stage shader pointers for VS. */
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sctx->shader_pointers_dirty &= ~SI_VS_SHADER_POINTER_MASK;
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sctx->vertex_buffer_pointer_dirty = false;
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si_draw_vbo(pipe, &info);
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pipe_resource_reference(&buf, NULL);
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}
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void si_trace_emit(struct si_context *sctx)
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@ -2306,6 +2306,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
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sctx->vs_shader.cso = sel;
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sctx->vs_shader.current = sel ? sel->first_variant : NULL;
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sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
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si_update_common_shader_state(sctx);
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si_update_vs_writes_viewport_index(sctx);
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