Commit Graph

140936 Commits

Author SHA1 Message Date
Erik Faye-Lund cef08f0557 llvmpipe: fix multisample lines again
This does a little bit better than what we did in 2c0a078fdb
("llvmpipe: fix multisample lines."), where parts of the diamond-exit
rule stuff was bypassed. But we should actually bypass *all* of the
diamond-exit rule stuff here instead.

The reason is that multisampled lines have a completely differently
specified set of rasterization rules, as per the OpenGL 4.6 core spec,
section 14.5.4 ("Line Multisample Rasterization").

So let's give multisampled lines their own geometry-generation codepath
instead.

This fixes the following dEQP tests:
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.primitives.lines
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
2021-06-11 09:57:58 +02:00
Erik Faye-Lund 9fa53d1f50 llvmpipe: consistently deal with post-rast state
There's no good reason why we peek into the rasterization state when
dealing with the point_quad_rasterization state, rather than set it
through lp_setup_set_point_state like other point-state.

Let's fix this up, and get rid of a needless NULL-check per primitive.

This makes the code a bit easier to read as well, and will help once
these conditions gets more complicated later on.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
2021-06-11 09:57:58 +02:00
Erik Faye-Lund 2812f030f1 llvmpipe: fix edge-rule logic for lines
In 2737abb44e, the handling of pixel-offsets and edge rules were
untangled, but one case was missed.

This fixes the following dEQP test-cases on VirGL + LLVMpipe
- dEQP-GLES2.functional.draw.random.10
- dEQP-GLES2.functional.draw.random.42
- dEQP-GLES3.functional.draw.random.105
- dEQP-GLES3.functional.draw.random.114
- dEQP-GLES3.functional.draw.random.135
- dEQP-GLES3.functional.draw.random.144
- dEQP-GLES3.functional.draw.random.155
- dEQP-GLES3.functional.draw.random.174
- dEQP-GLES3.functional.draw.random.206
- dEQP-GLES3.functional.draw.random.31
- dEQP-GLES3.functional.draw.random.43
- dEQP-GLES3.functional.draw.random.84
- dEQP-GLES31.functional.draw_indirect.random.20

...as well as these on Zink + Lavapipe:
- spec@nv_primitive_restart@primitive-restart-disable_vbo
- spec@nv_primitive_restart@primitive-restart-vbo_combined_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_index_only
- spec@nv_primitive_restart@primitive-restart-vbo_separate_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_vertex_only

Fixes: 2737abb44e ("gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
2021-06-11 09:57:56 +02:00
Yiwei Zhang d0d1b66d8e virgl: forward the host renderer hardware info
Some game engines rely on the real hardware info to adjust default
graphics quality and other attributes.

Prepend "virgl" to avoid app compat issues and to distinguish from
native platforms while giving engines/apps a chance to adjust graphics
defaults.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11179>
2021-06-11 06:47:02 +00:00
Georg Lehmann d3f735a249 ac: Enable 32bit predication on gfx9 with fw feature version 52.
Amdvlk does this as well and it passes the vulkan CTS on renoir.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
2021-06-11 06:07:10 +00:00
Georg Lehmann fc437ef944 ac: Enable 32bit predication on gfx10.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
2021-06-11 06:07:10 +00:00
Georg Lehmann a41ba20cbd ac: Check me_fw_feature for 32bit predication on gfx10.3
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
2021-06-11 06:07:10 +00:00
Samuel Pitoiset 4026a07e74 radv: fix aligning the image offset by using align64()
This doesn't fix anything known. Found by inspection.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11302>
2021-06-11 07:35:32 +02:00
Mike Blumenkrantz 9fdb6f56e1 util/disk_cache: add nocopy variant of disk cache store function
this is a bit more convenient in some cases

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11304>
2021-06-11 03:09:22 +00:00
Yiwei Zhang 1b74a12ea0 egl/android: add aosp_nougat system/window.h back for back compat
Also layer ANativeWindow_* APIs on top of legacy APIs for api level less
than 26 in a new platform_android.h header.

v2: persist frozen system/window.h header

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11286>
2021-06-11 02:33:57 +00:00
Rob Clark 1a716f5f06 docs: Update freedreno features
Bring features.txt a bit more up to date.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
2021-06-11 01:47:22 +00:00
Rob Clark 5a32976a1d freedreno: Add missing valid range tracking for SSBOs/images
Normally TC takes care of this for us.  But we might as well not get it
wrong in cases where TC is disabled.

Reported-by: Alyssa Rosenzweig <alyssa@collabora.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
2021-06-11 01:47:22 +00:00
Rob Clark 476f86fcb2 freedreno/registers: add A5XX_RBBM_STATUS3 bit
Same bit as a6xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
2021-06-11 01:47:22 +00:00
Emma Anholt 71c59aa413 ci/piglit: Skip WGL on all the Linux runs.
We don't build the tests, since we don't have WGL.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
2021-06-10 23:45:36 +00:00
Emma Anholt ea25090aab ci/freedreno: Enable running all of piglit_gl for a530's manual test.
Otherwise the xfails will end up stale after piglit uprevs that change the
test set.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
2021-06-10 23:45:36 +00:00
Emma Anholt 53826932db ci: Update piglit and deqp/piglit-runner.
This brings in some major new features in the runner:

- piglit tests now include subtest reporting
- "-t" support for quick include-filtering of tests.
- piglit tests that crash after their result report are considered crashes.
- throws a nice error if you try to annotate the same failure twice
  (e.g. lvp's dEQP-VK.glsl.builtin.precision.pow.highp.vec2,Fail)

Since the runner catches piglit test bugs where the same subtest is run
twice, we also uprev piglit to pull in the fixes for those.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
2021-06-10 23:45:36 +00:00
Tomeu Vizoso e210ed60be ci/lava: Don't overwrite PIGLIT_REPLAY_EXTRA_ARGS
Other Piglit jobs will want different values for this env var.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
2021-06-10 21:05:48 +00:00
Daniel Stone 2745fec6b9 ci/lava: Add --dump-yaml option to submitter
Also useful for local development and testing.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
2021-06-10 21:05:48 +00:00
Daniel Stone d5673dacd6 ci/lava: Add validate-only mode to job submitter
Useful for development.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
2021-06-10 21:05:48 +00:00
Tomeu Vizoso eddd2d332c ci/lava: Improve error reporting in lava_job_submitter.py
I'm having trouble figuring out why this is breaking.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
2021-06-10 21:05:48 +00:00
Emma Anholt d5204e0657 ci/lava: Finish garbage-collecting the TEST_SUITE variable
We no longer name the template by the test suite being run.

Fixes: 93ec399b28 ("ci: Use a single template for LAVA jobs")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
2021-06-10 21:05:48 +00:00
Paulo Zanoni 7e96ea1294 iris: don't munmap NULL pointers
This is a regression, the previous commit had this check which was
removed in the patch mentioned below. What happens is that when we
have a buffer that's not mmapped and we try to bo_free it we get some
very funny backtraces. Easily reproducible with fullscreen
gputest.triangle.

Fixes: f62724ccac ("iris: Pick a single mmap mode (WB/WC) at BO allocation time")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4890
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11284>
2021-06-10 20:49:59 +00:00
Dave Airlie e8956abe16 iris: drop unused function declaration
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11306>
2021-06-10 20:33:49 +00:00
Hoe Hao Cheng 8343cb923d zink/codegen: clean the constructor of Extension up
the `functions` parameter is now unused, also rewrote some comments
since they are now outdated

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng bec1e8d3fd zink/codegen: allow conditional enabling of instance extensions
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng 5574868103 zink: use the dispatch tables
- removed all usage of GET_PROC_ADDR
- find-and-replaced all instances of `screen->vk_` to `screen->vk.`

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng 039078fe97 zink: slight refactor of load_device_extensions()
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng c3608e6ac0 zink/codegen: add zink_verify_*_extensions()
those are meant to be used with the dispatch tables, by checking whether
the functions added by the enabled extensions are actually loaded

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng 94fba09432 zink/codegen: split commands into three groups
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Hoe Hao Cheng ed2fb8099e zink: introduce vk_dispatch_table
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
2021-06-10 20:24:40 +00:00
Connor Abbott c88eb66814 ir3: Copy propagate immed/const to meta instructions
This is allowed with the new RA, and makes a huge difference in
preventing extra moves when preferential coloring doesn't work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott a61a9cd65d ir3: Insert output collects in the main shader
We were inserting them in what was NIR's end block with the "end"
instruction, which meant that the moves they generated couldn't be
scheduled with the rest of the last block as part of post-RA scheduling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott fa17295ebd ir3: Add simple CSE pass
RA currently can't handle a live value that's part of a vector and
introduces extra copies. This was espeically a problem for bary.f, where
the bary coords were being split and repeatedly re-collected. But this
could be a problem in other situations as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott b1a1de76e8 ir3/sched: Consider unused destinations when computing live effect
If an instruction's destination is unused, then we shouldn't penalize
it. For example, this helps us schedule atomic operations whose results
aren't read. This works around RA failures when CSE is enabled in some
robustness2 tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott ba8efeb7fa ir3/sched: Make collects count against tex/sfu limits
In a scenario where there are a lot of texture fetches with constant
coordinates, this prevents the scheduler from scheduling all the setup
instructions after the first group of textures has been scheduled
because they are the only non-syncing thing and scheduling them didn't
decrease tex_delay. Collects with immed/const sources will turn into
moves of those sources, so we should treat them the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott 8b15c2f30c ir3/sched: Don't schedule collect early
I don't think there was ever a good reason to do this, but when we start
folding constants/immediates into collect, this can become actively
harmful.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott 27593cb241 ir3: Remove right and left copy prop restrictions
This is leftover from the old RA, and inhibits copy propagation
unnecessarily with the new RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott 2f51379d03 ir3/ra: Add a validation pass
This helps catch tricky-to-debug bugs in RA, or helps rule them out.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott 0ffcb19b9d ir3: Rewrite register allocation
Switch to the new SSA-based register allocator.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott df9f41cc02 ir3: Expose occupancy calculation functions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:06 -07:00
Connor Abbott 3ac743c333 ir3: Add pass to lower arrays to SSA
This will be run right after nir->ir3. Even though we have SSA coming
out of NIR, we still need it for NIR registers, even though we keep the
original array around to insert false dependencies.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:24:04 -07:00
Connor Abbott d4b5a550ed ir3: Add dominance infrastructure
Mostly lifted from nir.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott 1f3546c9e2 ir3: Remove unused check_src_cond()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott c0789395e0 ir3/postsched: Don't use SSA source information
This was only used for calculating if a source is a tex or SFU
instruction, which is easily replacable. It's going away with the new
RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott c947475533 ir3/delay: Delete pre-RA repeat handling
It looks likely that any implementation of (rptN) in ir3 will have to
actually create (rptN) instructions after RA, which means that this can
be dropped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott 58d82add87 ir3: Rewrite delay calculation
The old delay calculation relied on the SSA information staying around,
and wouldn't work once we start introducing phi nodes and making
"normal" values defined in multiple blocks not array regs anymore.
What's worse is that properly inserting phi nodes when splitting live
ranges would make that code even more complicated, and this was the last
place post-RA that actually needed that information.

The new version only compares the physical registers of sources and
destinations. It works by going backwards up to a maximum number of
cycles, so it might be slightly slower when the definition is closer but
should be faster when it is farther away.

To avoid complicating the new method, the old method is kept around, but
only for pre-RA scheduling and it can therefore be drastically
simplified as the array case can be dropped.

ir3_delay_calc() is split into a few variants to avoid an explosion of
boolean arguments in users, especially now that merged_regs now has to
be passed to it.

The new method is a little more complicated when it comes to handling
(rptN), because both the assigner and consumer may be (rptN). This adds
some unit tests for those cases, in addition to dropping the to-SSA code
in the test harness since it's no longer needed.

Finally, ir3_legalize has to be switched to using physical registers for
the branch condition. This was the one place where IR3_REG_SSA remained
after RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott c0823a2d31 ir3: Make branch conditions non-SSA
In particular, make sure they have a physreg assigned. This was the last
place after RA where SSA registers were created, which won't work with
the new post-RA delay calculation that relies on the physreg.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott fc7402b4cf ir3: Add reg_elems(), reg_elem_size(), and reg_size()
For working with registers in units of half-regs in the new RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott 890de1a436 ir3/delay: Fix full->half and half->full delay
The current compiler never does this, but the new compiler will start to
in mergeregs mode. There is an extra penalty for this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00
Connor Abbott 9ad83f51eb ir3: Add ir3_register::array.base
There were two different approaches I saw in the post-RA code for
figuring out what regiser range a relative access touched:

1. Use reg->array.offset and reg->array.size. This is wrong in case
   reg->array.offset was non-zero before RA, because array.size is
   the size of the whole array and array.offset has the const offset
   within the array baked in.
2. Lookup the array from the array ID and use the base + range there.
   This is correct, but won't work with the new RA, where an array might
   not always be assigned to the same register.

This replaces both methods with a new ir3_register::array.base field,
and switches all the users I could find to it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10 12:20:38 -07:00