882c18bf1c
gallium/radeon: clean up a misleading statement from the old days
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-07 19:38:43 +02:00
66176e6f14
radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE
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It's always good to have fewer decompress blits.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-07 19:38:42 +02:00
b40d8026fa
gallium/radeon: subclass threaded_transfer
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v2: use assert on rtransfer->b.staging
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
b4fc399c08
gallium/radeon: subclass threaded_resource
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
8b5485957e
gallium/radeon: unwrap a context if we get a wrapped one
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
854ed47f3e
radeonsi: mark fast-cleared textures as compressed when dirtying
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There are a bunch of piglit fast clear tests that regressed on SI, for
example ./bin/ext_framebuffer_multisample-fast-clear single-sample.
The problem is that a texture is bound as a framebuffer, cleared, and
then rendered from in a loop that loops through different clear colors.
The texture is never rebound during all this, so the change to
tex->dirty_level_mask during fast clear was not taken into account
when checking for compressed textures.
I have considered simply reverting the problematic commit. However,
I think this solution is better. It does require looping through all
bound textures after a fast clear, but the alternative would require
visiting more textures needless on every draw. Draws are much more
common than clears.
Note that the rendering feedback loop rules do not apply here, because
the framebuffer binding is changed between the glClear and the draw
that samples from the texture that was cleared.
Fixes: bdd6449769
2017-05-08 17:42:16 +02:00
744317c9d2
radeonsi/gfx9: allow CMASK fast clear with RB+
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
6ab2042761
radeonsi/gfx9: fix and enable single-sample CMASK fast clear
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
35aaccaf81
radeonsi/gfx9: fix linear mipmap CPU access
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
8c7d1ded19
radeonsi: decompress DCC in set_framebuffer_state instead of create_surface (v2)
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for threaded gallium, which can't use pipe_context in create_surface
v2: don't add a new decompress helper function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 20:57:53 +02:00
83d3e6fbff
radeonsi: fix an unused-variable warning in a release build
2017-03-30 17:22:25 +02:00
3b1934d9b6
gallium/radeon: s/dcc_disable/disable_dcc/
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-03-30 16:09:39 +02:00
a955ee788f
gallium/radeon: add and use a new helper vi_dcc_enabled
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-03-30 16:09:37 +02:00
474468fbf9
radeonsi/gfx9: disable features that don't work
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
7695ea0c02
radeonsi/gfx9: add linear address computations for texture transfers
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
7d88233f84
radeonsi/gfx9: handle pitch and offset overrides for texture_from_handle
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
de55e57e29
radeonsi/gfx9: set/validate GFX9 BO metadata
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
bd1da6b339
radeonsi/gfx9: add radeon_surf.gfx9.surf_offset
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
405bacd820
radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
272b50a6f4
radeonsi/gfx9: do DCC clears on non-mipmapped textures only
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
aba8e0ea68
radeonsi/gfx9: update can_sample_z/s flags
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
054dcbe42c
radeonsi/gfx9: pass correct parameters to buffer_get_handle
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
710aaed52b
radeonsi/gfx9: update si_set_optimal_micro_tile_mode
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
7fcad40ca5
radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE
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GFX9 supports this with all modes except linear.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
6f09b0d076
radeonsi/gfx9: update HTILE/CMASK/FMASK allocators
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
a0e8b73594
radeonsi/gfx9: update r600_print_texture_info
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
b25d7c2cbf
gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
ba2e7c68ce
gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
641b79774a
radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
6d21fd51b6
radeonsi/gfx9: disable RB+ on Vega10
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
04e6977e5d
gallium/radeon: reference pipe_resource in pipe_transfer
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for threaded gallium
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-03-17 18:30:21 +01:00
628e84a58f
gallium/util: replace pipe_mutex_unlock() with mtx_unlock()
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pipe_mutex_unlock() was made unnecessary with fd33a6bcd7
2017-03-07 08:53:05 +11:00
ba72554f3e
gallium/util: replace pipe_mutex_lock() with mtx_lock()
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replace pipe_mutex_lock() was made unnecessary with fd33a6bcd7
2017-03-07 08:52:38 +11:00
45240ce598
radeonsi: use R600_RESOURCE_FLAG_UNMAPPABLE where it's desirable
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-18 01:22:08 +01:00
c196efcf03
gallium/radeon: add an assertion to texture_transfer_map for app bugs
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Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
2017-02-14 21:47:51 +01:00
43a2ba1b7d
gallium/radeon: use staging for texture read mappings from GTT WC
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-10 11:27:50 +01:00
f8bc628b2c
gallium/radeon: merge dirty_fb_counter and dirty_tex_descriptor_counter
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to simplify things in draw_vbo a little
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-30 17:45:29 +01:00
7b32ae4df5
gallium/radeon: adjust the rule for using the LINEAR_ALIGNED layout
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-23 23:43:38 +01:00
9a3296bf1c
radeonsi: use SDMA for initial clearing of DCC/CMASK/HTILE on CIK-VI
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-05 18:43:23 +01:00
49fa4a4e60
gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE
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FORCE_TILING should disable it. It has no effect now, but that may change
soon.
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-21 21:44:35 +01:00
ce3f453f01
radeonsi: fix r600_texture::tc_compatible_htile
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htile_size is now always non-zero if HTILE is allocated.
It seems to have caused no issues.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-10 18:34:55 +01:00
7786f8c635
gallium/radeon: add enum radeon_micro_mode
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
1a4e0162fc
gallium/radeon: make it clear that DRM 2.x.x fast clear constraint is CIK-only
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
e3697b4be6
gallium/radeon: remove r600_surface::level_info
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
bf4d102ea3
gallium/radeon: add radeon_surf::is_linear
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
e9c76eeeaa
gallium/radeon: remove radeon_surf_level::pitch_bytes
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
c66a550385
gallium/radeon: don't call u_format helpers if we have that info already
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
692f2640ab
gallium/radeon: replace radeon_surf_info::dcc_enabled with num_dcc_levels
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
29144d0f34
gallium/radeon: stop using PIPE_BIND_CUSTOM
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it has no effect whatsoever
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
3dc78c33a9
gallium/radeon: remove unused r600_cmask_info members
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
Nicolai Hähnle
Timothy Arceri