Commit Graph

3376 Commits

Author SHA1 Message Date
Rob Clark c2c2da91a8 freedreno/a6xx: Do clip-plane lowering in backend
Our GS-lowered-to-quasi-VS confuses core nir passes, so handle clip-
plane lowering ourself.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 8f77187e3e freedreno/ir3: Fix GS clip-plane lowering
And also handle tess.  In all cases, we want to use the VS lowering pass
on the last geometry stage.  We don't make a special exception for GS
like other drivers, because GS gets lowered into a quasi-VS.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark f2d9805f9b freedreno/ir3: Add more tess varying slots
Fixes some piglits that I stumbled across by mistake.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark ff22be1110 freedreno/ir3: Copy vars if needed on EndPrimitive()
If we didn't EmitPrimitive() then the shadow (old) outputs would not
get copied to the emit temps (to eventually be copied back to the real
outputs.  This isn't so bad except that means the realy vertex_flags
output has an undefined value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 1fdddb1424 freedreno/ir3: Add copy_vars() helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 5434de7ab6 freedreno/ir3: Don't lower_gs multiple times
At least with gallium, this can be called multiple times via
pipe_screen::finalize_nir().  But it is not designed to be called
multiple times, and can result in vertex_flags getting 'optimized'
away.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6720
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 62c5d428bc turnip: assert valid vertex_flag reg
If this somehow gets optimized out, the GS will run forever.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Danylo Piliaiev bf4c160909 tu: Fix prim gen query and pipeline stats query interaction
Fixed:
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT was able to stop prim counter
  when pipeline stats query is running.
  - This may have happened when prim gen query was in secondary cmdbuf.
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT counting geometry in each tile.
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT counting geometry in each tile
  when pipeline stats query is started inside prim gen query and inside
  a renderpass.

The matter of VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT and pipeline stats
interaction is solved by tracking whether pipeline stats query is
running both on CPU (for non secondary cmdbuf case) and on GPU (for
secondary cmdbuf).

Note, prim gen query is not allowed with secondary command buffers, so
only pipeline stats query is tracked on gpu.
See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3142

Counting geometry per each tile is solved by:
- Conditionally executing START/STOP_PRIMITIVE_CTRS to not run in tiling
  pass. Solves the case when prim gen query is inside a renderpass.
- Stop prim counters before executing `draw_cs` and restarting them
  afterwards. Solves prim gen query being outside a renderpass.

Fixes GL CTS tests with Zink + `TU_DEBUG=gmem`:
 GTF-GL46.gtf30.GL3Tests.transform_feedback.transform_feedback_max_separate
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_basic
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_framebuffer
 GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_streams_overflow
 GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_streams_queried
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_states

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6602

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17163>
2022-07-08 11:14:18 +03:00
Danylo Piliaiev 465e7c303b tu,freedreno: Refactored START/STOP events for pipeline stats
For a5xx+ renamed:
- RST_PIX_CNT -> START_FRAGMENT_CTRS
- RST_VTX_CNT -> STOP_FRAGMENT_CTRS
- TILE_FLUSH  -> START_COMPUTE_CTRS
- STAT_EVENT  -> STOP_COMPUTE_CTRS
I'm not sure about a5xx itself but I'll take a chance of it being
similar to a6xx in this regard.

Knowing this emit_begin_stat_query/emit_end_stat_query can now emit
only events that are needed for the pool's flags.

Also primitive generated query clearly doesn't need fragment and
compute counters.

Passes tests:
 dEQP-VK.query_pool.statistics_query.*
 dEQP-VK.transform_feedback.primitives_generated_query.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17163>
2022-07-08 11:14:18 +03:00
Pierre-Eric Pelloux-Prayer 8856379a03 mesa/st: don't guess the internal format if it's known
This fixes tests using imageLoad/imageStore on texture
created using glEGLImageTargetTexture2DOES.

Before this change, the format was guessed as GL_RGBA,
which would be rejected by _mesa_get_shader_image_format.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
2022-07-07 12:25:05 +00:00
Emma Anholt 00ad29dd23 ci: Uprev deqp to 1.3.3.0.
New tests, dEQP line rasterization test fix that lets Intel pass.

Clears out bogus xfails from 1.3.2.0 uprev on a630, which I suspect were
"we lost the device twice on a full run once, and those fails got pasted
in without checking if it happened a full run again" (since we haven't
seen them in other full run attempts).

Also clears out the a630 vk asan xfails (essentially all tests run) by
turning off leak detection which was just catching leaks in vkcts.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17304>
2022-07-05 17:02:33 +00:00
Emma Anholt 01988667fd ir3: Retire the cp postsched pass now that we do RA in SSA.
Before, we needed CP post-sched to copy-propagate references to NIR
registers produced by out-of-ssa.  Now that we're in SSA, this pass ends
up not doing anything useful, and actually gets in the way by occasionally
creating a cycle in the DAG.

The entire shader-db impact is:

instructions HURT:   shaders/closed/steam/tropico-5/78.shader_test FRAG: 238 -> 242 (1.68%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17320>
2022-07-04 22:15:58 +00:00
David Heidelberg fb2266631f Revert "ci/freedreno: temporary disable AmnesiaTDD"
This reverts commit f77695d13f.

Acked-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17353>
2022-07-04 18:46:57 +02:00
Rob Clark 9e1bf8e7ac freedreno/registers: Small cleanup
Whitespace fix plus move a couple regs that ended split apart from the
rest of the VFD regs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>
2022-07-03 23:20:46 +00:00
Rob Clark bc6f1afc79 freedreno: Add pkt4 assert
Add assert to catch places where we overflow max PKT4 size

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>
2022-07-03 23:20:46 +00:00
Jonathan Marek b41620f9ed freedreno/registers: add missing varset="chip" for new enum values
Fixes: de8c769d11 ("freedreno/registers: add a7xx registers for drm/msm kernel driver")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6788
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17351>
2022-07-03 18:01:17 +00:00
David Heidelberg 1bcb883ea5 ci/freedreno: disable SpecOps trace, each run flaky
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17336>
2022-07-01 15:47:09 +00:00
Jonathan Marek de8c769d11 freedreno/registers: add a7xx registers for drm/msm kernel driver
Most of this is taken directly from the downstream kernel driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602>
2022-07-01 15:11:28 +00:00
David Heidelberg 6f2a991f78 ci/freedreno: disable Stellaris trace
Revert when it gets fixed on CI runner (works on OnePlus 6T with
5.18 kernel).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg f77695d13f ci/freedreno: temporary disable AmnesiaTDD
Revert when https://gitlab.freedesktop.org/mesa/mesa/-/issues/6763 get fixed.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg 74da4dc216 ci/freedreno: add more restricted traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:03 +02:00
Danylo Piliaiev c655387a02 ir3: Use NIR's info.writes_memory to detect when when to force late-z
Better than maintaining our old checks.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16818>
2022-07-01 11:37:17 +00:00
Emma Anholt 05b41f9207 ci/freedreno: Filter when we run test jobs for VK or GL changes.
Not only runs less testing when only one driver is impacted, but also
makes sure zink+turnip is turned off when the farm is.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>
2022-06-30 18:31:21 +00:00
Hyunjun Ko f4b72fa26d turnip: keep the depth_clip_disable state at the pipeline builder.
So we could later decide whether to enable Z_CLIP_DISABLE on not.

Closes: #6732

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>
2022-06-30 01:08:17 +00:00
Hyunjun Ko 6cb41c5188 freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE
UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>
2022-06-30 01:08:17 +00:00
Hyunjun Ko d2e769c1b6 turnip: fix wrong size for lrz cs when lrz_track_quirk is enabled.
Fixes: 4b5f0d98fd ("tu: Overhaul LRZ, implement on-GPU dir tracking and
LRZ fast-clear")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17289>
2022-06-29 11:15:23 +00:00
Connor Abbott 8183a728a2 tu: Fix stencil border color with has_z24uint_s8uint
On a650+ we use the new Z24UINT_S8UINT format to sample the stencil
aspect of D24S8, which returns stencil in the second component and also
uses the second integer component for the border color. However Vulkan
mandates that the first component is used for the stencil border color.
There's no workaround we know of, so we have to fall back to the old
behavior where there is a workaround. If we know the format, we can
fixup the border color ourselves though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott e135c03446 freedreno/fdl: Note border color constraints
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 4901a8f86e freedreno/a6xx: Use fdl format swizzle
This makes sure that we use a consistent swizzle between computing the
border color and the texture descriptor, and lets us delete the gallium
version.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 39c64a4b53 freedreno/a6xx: Fix border color swizzling
From the API's point of view, border color replacement looks like this:

       --------------------
       | API Border Color |
       --------------------
               |
-----------    |    ----------------      ----------
| API fmt |-------->| User Swizzle |----->| Shader |
-----------         ----------------      ----------

From the HW point of view, it looks like this:

                    -------------------
                    | HW Border Color |
                    -------------------
                             |
----------     -----------   |   ---------------      ----------
| HW fmt |-----| HW swap |------>| Tex Swizzle |----->| Shader |
----------     -----------       ---------------      ----------

When the HW fmt + HW swap isn't enough to represent an API format, we
need to prepend our own swizzle to the the user's swizzle, so the tex
swizzle is a "format swizzle" composed with the user swizzle. However,
we don't want this format swizzle to be applied to border colors, so
there's a workaround in freedreno which is meant to undo the format
swizzle so that the HW border color with the format swizzle applied
equals the API border color, and everything is ok. However, on a6xx at
least it was incorrectly undoing the entire tex swizzle. This broke
border color with a user swizzle, because it was now effectively not
getting applied for the border color. It also made it seem like the user
swizzle is required for the workaround, which would have implications
for VK_EXT_border_color_swizzle with turnip, but it's not.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 2a928ae325 freedreno/a6xx: Document border color/swizzle interaction
Make it clear that the swap happens before border color replacment but
the swizzle happens after.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Danylo Piliaiev 4b5f0d98fd tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear
On-GPU LRZ direction tracking allows LRZ to support secondary cmdbufs,
reusing LRZ between renderpasses, and in future to support LRZ when
VK_KHR_dynamic_rendering is used.

With on-gpu tracking we have to be careful keeping LRZ state in sync
with underlying depth image, which means we should invalidate LRZ
when underlying image is changed or the view of image is different
from previous renderpass.

All of this resulted in LRZ logic being thinly spread through the code,
making it hard to understand. So most of it was moved to tu_lrz.c.

For more details on past and new LRZ features see comment at the
top of tu_lrz.c.

Note about blob:
- Blob is much more happy to do LRZ_FLUSH, it flushes at the start
  of the renderpass, after binning, and at the end of the renderpass.
- Blob seem not to care about changes in depth image done via
  vkCmdCopyImage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6347

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Danylo Piliaiev 70f1d70ddd freedreno: document GRAS_UNKNOWN_810A
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Connor Abbott 1cd91fdec3 freedreno: Document a650-specific CP_REG_WRITE flag
v2: Danylo: clarified previously unknown GRAS_LRZ_CNTL field.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Danylo Piliaiev 5592c366cf freedreno: Document rest of GRAS_LRZ_CNTL, clarify UNK_25 event
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Boris Brezillon 02384ca13c tu: Use vk_pipeline_hash_shader_stage()
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17186>
2022-06-28 09:07:32 +00:00
Emma Anholt f93bee19d9 ci/turnip: Trim the a630 VK run a bit.
We have a lot of spilling coverage in a618 pre-merge, don't do it all (~2
minutes) here.  Also, force-gmem touch testing should probably test less than
the default run does!

This should help make up for having added the tu-zink run.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Emma Anholt 523ed9521b ci/turnip: Test traces on turnip using zink.
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Emma Anholt 8e53194f44 ci/freedreno: Add vulkan+gl integration testing in piglit.
The libvulkan-dev was needed for building zink, which ended up turning on
the vulkan tests in piglit.  Split them out here.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Danylo Piliaiev 5aeefe8d75 tu: Don't count 3d blits in QUERY_TYPE_PRIMITIVES_GENERATED
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
2022-06-24 14:10:56 +00:00
Danylo Piliaiev 97ef19e6ce tu: Use hw binning or sysmem with QUERY_TYPE_PRIMITIVES_GENERATED
Without hw binning in gmem primitives generated query result could be
multiplied by tile count, which is not expected by OpenGL users for
GL_PRIMITIVES_GENERATED.

See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3131

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
2022-06-24 14:10:56 +00:00
Vinson Lee b1df00cb79 tu: Check dereferenced value of rop_reads_dst.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking rop_reads_dst suggests that it may be
null, but it has already been dereferenced on all paths leading to the
check.

Fixes: 94be0dd0b8 ("tu: Implement extendedDynamicState2LogicOp")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17099>
2022-06-23 11:11:56 +00:00
Connor Abbott 7d706af76b ir3: Fix vectorizer condition for SSBOs
SSBO access works very differently from UBO access. Straddling
loads/stores isn't an issue, loads/stores instead must be aligned to the
element size and can have up to 4 components.

We support 16-bit access with SSBOs on a650+, and sometimes the
vectorizer tries to create a misaligned 32-bit access when combining
32-bit and 16-bit accesses. The UBO-focused logic didn't reject this,
which is now fixed. This fixes a number of VK-CTS regressions on a650+.

Fixes: bf49d4a084 ("freedreno/ir3: Enable load/store vectorization for SSBO access, too.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17040>
2022-06-23 10:46:31 +00:00
Jason Ekstrand deb36dc6c2 turnip: Use the new border color helpers
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15359>
2022-06-23 00:01:41 +00:00
Emma Anholt 13bf36588d ci/bare-metal: Consolidate needs declarations in .baremetal-test-*.
We had it set up for arm64 asan already, do it for everyone else too.  In
cleaning up the duplication, this fixes a pasteo in rpi3 which had the
"artifacts: false" on the wrong job, causing it to do a slow download of
the mesa build from gitlab.

Doing this required also moving the ".use-debian/arm_test" in as well, so
that its "needs:" didn't overwrite ours if it appeared after us in the
consumer's "extends:"

Should save about 20 seconds on rpi3 jobs.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17146>
2022-06-22 20:59:54 +00:00
Emma Anholt 69cad6dcb7 ci/freedreno: Turn a530 back on by default and update expectations.
I think it should be fixed since I redid how we manage serial around
restarts.  Haven't seen a fail in the manual runs I've done.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Emma Anholt 4e3c51cbd8 freedreno/a5xx: Set the buffer bit appropriately in XS_CTRL_REG0.
This seems to be how the bit gets used, from grepping my blob traces.
Hopefully this helps stabilize some stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Emma Anholt 6cf2b24eaf freedreno/ir3: Disable image/ssbo 16-bit conversion folding pre-a6xx.
I don't see it in blob dumps, and the reordered args tripped up validation.

Fixes: 49dc60efa1 ("freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Connor Abbott d455838081 tu: Fix linemode for tessellation with isolines
Fixes: 542211676c ("turnip: enable VK_EXT_line_rasterization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17190>
2022-06-22 17:57:53 +00:00
Danylo Piliaiev f1c1b9687e tu: Do not expose storage image/buffer features for PACK16 formats
We don't support storing into them.

Fixes GL CTS tests running through ZINK:
 KHR-GL46.packed_pixels.pbo_rectangle.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17168>
2022-06-22 14:39:47 +00:00