Commit Graph

109461 Commits

Author SHA1 Message Date
Rob Clark bf5a92811d freedreno/ir3: disable early-z for SSBO/image writes
Fixes:

dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_stencil
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_stencil_fbo

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-22 08:53:28 -04:00
Rob Clark dbac1a80d1 freedreno/ir3: rename has_kill to no_earlyz
There are other cases where we need to disable early-z, like image
writes.  So rename to something more generic.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-22 08:53:28 -04:00
Rhys Perry f736250ab4 ac/nir: implement 16-bit pack/unpack opcodes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-03-22 12:50:16 +01:00
Lionel Landwerlin 87dadbce5b vulkan/overlay: improve error reporting
We can show the actual command & line where the failure happened

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-22 11:26:04 +00:00
Lionel Landwerlin 9f3727351d vulkan/overlay: check return value of swapchain get images
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-22 11:26:01 +00:00
Lionel Landwerlin 1fbf355597 vulkan/overlay: silence validation layer warnings
v2: Drop call to FreeDescriptorSet

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-22 11:25:58 +00:00
Lionel Landwerlin de14107741 vulkan/overlay: properly register layer object with loader
This is required by the validation layers if we want to validate the
commands inserted by the overlay layer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-22 11:25:55 +00:00
Józef Kucia c077d5d7de radv: Fix driverUUID
Fixes: 14cad8786a ("radv: generate the same driver UUID as radeonsi")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-03-22 08:57:16 +01:00
Danylo Piliaiev ea9bde151f
glsl: Cross validate variable's invariance by explicit invariance only
'invariant' qualifier is propagated on variables which are used
to calculate other invariant variables, however when we are matching
variable's declarations we should take into account only explicitly
declared invariance because invariance propagation is an implementation
specific detail.

Thus new flag is added to ir_variable_data which indicates 'invariant'
qualifier being explicitly set in the shader.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100316
Fixes: 89b60492 ('glsl: Add a pass to propagate the "invariant" and
  "precise" qualifiers')

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-03-21 23:28:08 -07:00
Józef Kucia 1d996ef714 mesa: Fix GL_NUM_DEVICE_UUIDS_EXT
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-22 07:37:14 +02:00
Kenneth Graunke 66c100a8d6 iris: Skip resolves and flushes altogether if unnecessary
Improves drawoverhead baseline scores by 1.17x.
2019-03-21 20:28:17 -07:00
Kenneth Graunke 365886ebe1 iris: Skip framebuffer resolve tracking if framebuffer isn't dirty
Improves drawoverhead baseline score by 1.86x.
2019-03-21 20:28:17 -07:00
Kenneth Graunke 1d05d24b1d iris: Skip input resolve handling if bindings haven't changed
This brings the drawoverhead 16 Tex w/ no state change score from
22% of baseline to 97% of baseline.
2019-03-21 20:28:17 -07:00
Kenneth Graunke a342f2deb1 iris: Fix util_vma_heap_init size for IRIS_MEMZONE_SHADER
Fixes assertions when disabling bucket allocators.
2019-03-21 19:07:17 -07:00
Dave Airlie 9dd92d08a5 softpipe: fix integer texture swizzling for 1 vs 1.0f
The swizzling was putting float one in not integer 1.

This fixes a lot of arb_texture_view-rendering-formats cases.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:35 +10:00
Dave Airlie aae5ba72ab softpipe: remove shadow_ref assert.
I don't think this really buys us anything and TG4 with cubemap arrays
falls over because sampler == 2, but otherwise works fine.

Fixes:
./bin/textureGather fs shadow r  CubeArray repeat

on softpipe with ARB_gpu_shader5 enabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:29 +10:00
Dave Airlie 8dc8b1361a softpipe: handle 32-bit bitfield inserts
Fixes piglits if ARB_gpu_shader5 is enabled

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:26 +10:00
Dave Airlie 7b7cb1bc35 softpipe: fix 32-bit bitfield extract
These didn't deal with the width == 32 case that TGSI is defined with.

Fixes piglit tests if ARB_gpu_shader5 is enabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:21 +10:00
Timothy Arceri a1bd9dd5bc nir: fix opt_if_loop_last_continue()
Rather than skipping code that looked like this:

     loop {
        ...
        if (cond) {
           do_work_1();
           continue;
        } else {
           break;
        }
        do_work_2();
     }

Previously we would turn this into:

     loop {
        ...
        if (cond) {
           do_work_1();
           continue;
        } else {
           do_work_2();
           break;
        }
     }

This was clearly wrong. This change checks for this case and makes
sure we now leave it for nir_opt_dead_cf() to clean up.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-03-22 09:58:18 +11:00
Gurchetan Singh 620df57dbb anv: fix build on Nougat
AHardwareBuffer is only available on O and above.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-21 15:36:39 -07:00
Gurchetan Singh 139f908d8f anv: move anv_GetMemoryAndroidHardwareBufferANDROID up a bit
No functional change, just makes the next patch a little easier.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-21 15:36:39 -07:00
Gurchetan Singh b070861045 configure.ac / meson: depend on libnativewindow when appropriate
libnativewindow is only available on O or greater, and it's
required for some features.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-03-21 15:36:39 -07:00
Eric Anholt bfed0a7099 v3d: Remove some dead members of struct v3d_compile.
These are more vc4 leftovers.
2019-03-21 14:20:50 -07:00
Eric Anholt 16f2770eb4 v3d: Upload all of UBO[0] if any indirect load occurs.
The idea was that we could skip uploading the constant-indexed uniform
data and just upload the uniforms that are variably-indexed.  However,
since the VS bin and render shaders may have a different set of uniforms
used, this meant that we had to upload the UBO for each of them.  The
first case is generally a fairly small impact (usually the uniform array
is the most space, other than a couple of FSes in shader-db), while the
second is a larger impact: 3DMMES2 was uploading 38k/frame of uniforms
instead of 18k.

Given that the optimization is of dubious value, has a big downside, and
is quite a bit of code, just drop it.  No change in shader-db.  No change
on 3DMMES2 (n=15).
2019-03-21 14:20:50 -07:00
Eric Anholt 320e96bace v3d: Move constant offsets to UBO addresses into the main uniform stream.
We'd end up with the constant offset in the uniform stream anyway, since
they're bigger than small immediates.  Avoids the extra uniforms and adds
in the shader in favor of just adding once on the CPU.

shader-db:
total instructions in shared programs: 6496865 -> 6494851 (-0.03%)
total uniforms in shared programs: 2119511 -> 2117243 (-0.11%)
2019-03-21 14:20:50 -07:00
Eric Anholt c36d2793ec v3d: Rename v3d_tmu_config_data to v3d_unit_data.
I want to reuse this for encoding small constant UBO/SSBO offsets into the
uniform stream to reduce the extra uniform loads and adds for the small
constant offsets.
2019-03-21 14:20:50 -07:00
Benjamin Gordon b30aad552c configure.ac/meson.build: Add options for library suffixes
When building the Chrome OS Android container, we need to build copies
of mesa that don't conflict with the Android system-supplied libraries.
This adds options to create suffixed versions of EGL and GLES libraries:

libEGL.so -> libEGL${egl-lib-suffix}.so
libGLESv1_CM.so -> libGLESv1_CM${gles-lib-suffix}.so
libGLESv2.so -> libGLES${gles-lib-suffix}.so

This is similar to what happens when --enable-libglvnd is specified, but
without the side effects of linking against libglvnd.  To avoid
unexpected clashes with the suffixed appended by libglvnd, make it an
error to specify both --enable-libglvnd and --with-egl-lib-suffix.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-21 10:18:31 -07:00
Kenneth Graunke e426c3a6cb nir: Record non-vector/scalar varyings as unmovable when compacting
In some cases, we can end up with varying structs that aren't split to
their member variables.  nir_compact_varyings attempted to record these
as unmovable, so it would leave them be.  Unfortunately, it didn't do
it right for non-vector/scalar types.  It set the mask to:

   ((1 << (elements * dmul)) - 1) << var->data.location_frac

where elements is the number of vector elements.  For structures and
other non-vector/scalars, elements is 0...so the whole mask became 0.

This caused nir_compact_varyings to assign other varyings on top of
the structure varying's location (as it appeared to take up no space).

To combat this, we just set elements to 4 for non-vector/scalar types,
so that the entire slot gets marked as unmovable.

Fixes KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_in on iris.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-21 16:03:58 +00:00
Rob Clark 6e781a01b9 freedreno/ir3: dynamic UBO indexing vs 64b pointers
Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment
and similar things with multiple UBOs

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 2e01c534f4 freedreno/ir3: fix bit_count
Seems like it can only work 16b at a time.  Fixes
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*

TODO need to check if this limitation applies to a3xx as well.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 3d8349048b freedreno/ir3: additional lowering
For some things that show up when we expose higher glsl

TODO check blob traces to see if we have instructions for some of this?
I guess we don't but worth a check..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark bcd81d2387 freedreno/ir3: optimize sam.s2en to sam
Detect when sampler/texture idx are immediate and switch to non s2en
encoding.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 1443694ee5 freedreno/ir3: enable indirect tex/samp (sam.s2en)
For now it uses indirect for everything.  The next step is for the
ir3_cp pass to detect the case that tex and samp idx are immediate
and convert the sam instruction back to the non .s2en variant.  But
doing that in a following patch so we can shake out the bugs with
.s2en more easily.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 1088b788d8 freedreno/ir3: find # of samplers from uniform vars
When we have indirect samplers, we cannot tell the max sampler
referenced.  Instead just refer to the number of sampler uniforms.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark d4cbc94685 nir: move gls_type_get_{sampler,image}_count()
I need at least the sampler variant in ir3..

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-21 09:13:05 -04:00
Rob Clark 8eb16ae8bf freedreno/ir3: fix regmask for merged regs
On a6xx+ with half-regs conflicting with full-regs, the legalize pass
needs to set appropriate sync bits, such as (sy), on writes to full regs
that conflict with half regs, and visa-versa.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 1dffb089f9 freedreno/ir3: fix sam.s2en encoding
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 45b7a581b4 freedreno/ir3: fix sam.s2en decoding
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark 2d31cf9d3b freedreno/ir3/ra: fix half-class conflicts
On a6xx, half-regs conflict with full-regs.  But we were only setting up
conflicts for the first class (ie. scalar, but not hvec2/hvec3/hvec4),
resulting in higher half-reg classes getting assigned to regs that
overwrite full-regs.

Noticed while trying to enable indirect-sampler (sam.s2en) which uses an
hvec2 argument to pass the sampler/tex index.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Rob Clark cc5ca9391c freedreno/ir3 better cat6 encoding detection
These two bits seem to be a better way to detect which encoding we are
looking at.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-21 09:13:05 -04:00
Samuel Pitoiset 00327f827f ac: fix incorrect argument type for tbuffer.{load,store} with LLVM 7
GLC/SLC are boolean.

This fixes the following LLVM error when checkir is set:
Intrinsic has incorrect argument type!
void (i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32)* @llvm.amdgcn.tbuffer.store.i32

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
2019-03-21 14:02:00 +01:00
Samuel Pitoiset 20cac1f498 ac: fix 16-bit shifts
This fixes the following LLVM error when ckeckir is set:
Type too small for ZExt

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
2019-03-21 14:01:58 +01:00
Samuel Pitoiset 2ac5c5c1b5 ac: add 16-bit support to fract
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-21 12:13:09 +01:00
Samuel Pitoiset 0eb1478ac2 ac: add 16-bit support fo fsign
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-21 12:13:07 +01:00
Samuel Pitoiset ff11c9dcc7 ac: add f16_0 and f16_1 constants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-21 12:13:05 +01:00
Timothy Arceri 427a6fee43 nir: only override previous alu during loop analysis if supported
Users of this function expect alu to be a supported comparision
if the induction variable is not NULL. Since we attempt to
override the return values if the first limit is not a const, we
must make sure we are dealing with a valid comparision before
overriding the alu instruction.

Fixes an unreachable in inverse_comparison() with the game
Assasins Creed Odyssey.

Fixes: 3235a942c1 ("nir: find induction/limit vars in iand instructions")

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110216
2019-03-21 21:51:21 +11:00
Michel Dänzer 6d0a7f798c gitlab-ci: Use 8 CPU cores in autotools job
This cuts down the job runtime from ~9.5 to ~7 minutes with my personal
runner on an 8-core Ryzen 7 1700.

While this might result in slightly higher load on shared runners, it
should be OK, since libtool doesn't use the CPU cores as effectively as
e.g. ninja does; a significant part of the CPU load tends to be in bash
processes at any time, which should be relatively light on memory.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-21 09:58:31 +01:00
Michel Dänzer a2cce701e6 gitlab-ci: List some longer-running jobs before others of the same stage
This increases the chance of them running earlier, which can have an
impact on the total duration of the pipeline.

v2:
* Minor style fix-up to moved comment (Eric Anholt)

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Eric Anholt <eric@anholt.net>
2019-03-21 09:55:08 +01:00
Samuel Pitoiset db07f0554a radv: add missing initializations since VK_EXT_pipeline_creation_feedback
This fixes the world.

Fixes: 5f5ac19f13 ("radv: Implement VK_EXT_pipeline_creation_feedback.")"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-21 09:42:31 +01:00
Rhys Perry 037f11d42e radv: enable VK_KHR_8bit_storage
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-21 09:02:27 +01:00