Commit Graph

147497 Commits

Author SHA1 Message Date
Jesse Natalie 96012b686e d3d12: Handle import/export of fd shared handles
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie 31c7a04b47 winsys/d3d12: Populate winsys handle format
All other winsys handle users do so, and a future commit will
start caring about it.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie 2771fd4a3f gallium, windows: Use HANDLE instead of FD for external objects
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie 5bfbf4bec9 microsoft/compiler: Handle GLES external textures
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie 2188607014 d3d12: Support RGBX formats mapped to RGBA
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie ab9948997a d3d12: Support PIPE_CAP_MIXED_COLOR_DEPTH_BITS
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie e0576ec148 d3d12: Support BGRA 555 and 565 formats
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
2021-11-19 22:54:46 +00:00
Jesse Natalie d0bc4974fa android: Allow forcing softpipe
When dealing with swrast, there's two possibilities: If you have LLVM, you get
llvmpipe, which is pretty fast. If you don't, you get softpipe, which is slow,
but does have a couple nice qualities, like being smaller and not needing
executable memory for JIT.

If you're building a driver that requires LLVM like radeonsi then you need the
LLVM stub for the build to find LLVM. But for swrast, since it can mean either
softpipe/llvmpipe, you don't strictly need LLVM. So this just makes the
Android build files flexible like the Meson build files (where you can specify
-Dllvm=disabled even if LLVM is findable).

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
2021-11-19 21:21:35 +00:00
Jesse Natalie 33e5a4378e android,d3d12: Support using DirectX-Headers dependency from AOSP
Note that the Android build system apparently lowercases stuff,
so add a lowercase "directx-headers" dependency which is searched first,
before falling back to the proper-cased "DirectX-Headers" dependency.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
2021-11-19 21:21:35 +00:00
Jesse Natalie 6138b047e2 mesa/main, android: Log errors to logcat
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
2021-11-19 21:21:35 +00:00
Jesse Natalie 9e82a56745 android: Add a BOARD CFlags option so build can be customized
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
2021-11-19 21:21:35 +00:00
Mike Blumenkrantz 81cc94b8f0 zink: be consistent about waiting on context queue on context destroy
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
2021-11-19 18:56:10 +00:00
Mike Blumenkrantz e92b8956c7 zink: set batch state queue on creation
make this easier to find

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
2021-11-19 18:56:10 +00:00
Emma Anholt b8ffd7a888 freedreno/a5xx: Emit MSAA state for sysmem rendering, too.
This looked obviously wrong, we want to set the sample counts for sysmem
too just like we do on 6xx.  Turns out it fixes some piglits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
2021-11-19 17:24:11 +00:00
Emma Anholt 5071d39cb2 freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info.
Noticed while looking through my set of traces for where the average bit
might be.  Same spot as on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
2021-11-19 17:24:11 +00:00
Emma Anholt 1ef6465665 freedreno/a5xx: Define a5xx_2d_surf_info like a6xx has.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
2021-11-19 17:24:11 +00:00
Emma Anholt cad0b6e2e5 freedreno/a6xx: Disable sample averaging on non-ubwc z24s8 MSAA blits.
The fallback path we averages unorm textures, but if we don't have ubwc on
either then we can just cast them to uint which then just takes sample 0.

The proper UBWC format I think ends up averaging, though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
2021-11-19 17:24:11 +00:00
Emma Anholt 93eb697a8d freedreno/a6xx: Disable sample averaging on z/s or integer blits.
We can't generally force fd_blitter_blit() to not average in our fallback
blits, but this should at help some cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
2021-11-19 17:24:11 +00:00
Connor Abbott c98adc56f4 ir3/lower_pcopy: Fix bug with "illegal" copies and swaps
If the source and destination were within the same full register, like
hr90.x and hr90.y (which both map to r45.x), then we'd perform the
swap/copy with the wrong register. This broke
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35 once BDA is enabled.

Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
2021-11-19 16:59:54 +00:00
Connor Abbott 65da866ad9 ir3/lower_pcopy: Fix shr.b illegal copy lowering
The immediate shouldn't be half-reg because the other source isn't.
Fixes an assertion failure with
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35.

Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
2021-11-19 16:59:54 +00:00
Connor Abbott 9912c61362 ir3/spill: Support larger spill slot offset
This is required by
dEQP-VK.ssbo.phys.layout.random.all_shared_buffer.47, where we need to
spill a lot of pointers due to NIR CSE being a little too aggressive and
creating a large register pressure across basic blocks, too large to fit
within the boundaries of ldp/stp offsets.

Note that this will be a lot more difficult with support for "real
functions" because the base register will become unknown at compile
time. However this hack gets things working for the time being.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
2021-11-19 16:59:54 +00:00
Connor Abbott 29d3889bbb ir3/ra: Add missing asserts to ra_push_interval()
This would've caught the previous issue earlier. We checked that the
physreg made sense when inserting via ra_file_insert() but not
ra_push_interval() which is used for live-range splitting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
2021-11-19 16:59:54 +00:00
Connor Abbott 9d88b98b08 ir3/ra: Consider reg file size when swapping killed sources
Don't swap a 2-component vector of half-regs with a full reg if that
would result in the half regs going outside of the allowable half-reg
space.

Fixes: d4b5d2a020 ("ir3/ra: Use killed sources in register eviction")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
2021-11-19 16:59:54 +00:00
Jesse Natalie f9a46ad22a meson: Allow mismatching RTTI for MSVC
This might be safe to relax to all Windows compilers, but I didn't
test Clang or MinGW, so scoping to MSVC for now. For MSVC, this is
safe to mismatch, because the vftables are emitted into all objects
with "pick largest," and the definition with RTTI is larger than the
one without. This is different than the Itanium ABI, which only emits
one copy of the typeinfo in the object which defines the key method.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
2021-11-19 15:36:59 +00:00
Jesse Natalie ad86267412 meson: Don't override built-in cpp_rtti option, error if it's invalid
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
2021-11-19 15:36:59 +00:00
Lionel Landwerlin 21ec880bf9 anv: initialize anv_bo_sync base fields
v2: zalloc

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cbb13fae33 ("anv: Add a BO sync type")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13875>
2021-11-19 15:09:43 +00:00
Lionel Landwerlin 04bd5bb69b anv: don't try to close fd = -1
CID: 1464334

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13879>
2021-11-19 14:52:29 +00:00
Samuel Pitoiset ddbc84d5a0 radv: ignore the descriptor set layout when creating descriptor template
From the Vulkan spec:
    "This parameter is ignored if templateType is not
     VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET."

This fixes an assertion about the base object type when running Yuzu
with Vulkan validation layers enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13846>
2021-11-19 13:52:36 +00:00
Samuel Pitoiset 2436cafffe radv: allow TC-compat CMASK with storage images on GFX10+
Hardware seems to support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12173>
2021-11-19 13:30:40 +00:00
Mike Blumenkrantz 22d9d0f8b5 zink: add a compiler pass to scan for shader image use
other frontends and internal shaders won't set this

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13864>
2021-11-19 13:14:46 +00:00
Mike Blumenkrantz e386a57769 zink: explicitly init glsl
need this to be able to use other frontends

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13864>
2021-11-19 13:14:46 +00:00
Alejandro Piñeiro ff89dc3523 vulkan: move common format helpers to vk_format
v3dv, radv, and turnip are using several C&P format helpers (most of
them wrappers over util_format_description based helpers).  methods.

This commit moves the common helpers to the already existing common
vk_format.h. For the case of v3dv we were able to remove the vk_format
header. For turnip and radv, a local vk_format.h header remains, with
methods that are only used for those drivers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13858>
2021-11-19 12:23:19 +01:00
Samuel Pitoiset 04c90f292e util/queue: fix a data race detected by TSAN when finishing the queue
Thread sanitizer complains if it detects that the pthread_barrier
is destroyed when a thread might still blocked on the barrier.

Fix this by destroying the barrier only if pthread_barrier_wait
returns PTHREAD_BARRIER_SERIAL_THREAD which is the value for success.

In practice this shouldn't fix anything serious given that this code
is only called when the disk cache is destroyed.

Original patch from Timothy Arceri.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4342
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13861>
2021-11-19 09:02:23 +01:00
Qiang Yu cee1dd92bd glx/dri3: fix glXQueryContext does not return GLX_RENDER_TYPE value
Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13772>
2021-11-19 01:37:27 +00:00
Emma Anholt e277b13182 freedreno: Stop exposing MSAA image load/store on desktop GL.
GLES doesn't support it, and blob VK doesn't support it.  We could
theoretically lower it, but don't bother since it's not required.  Fixes
various piglit image load/store tests.

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13852>
2021-11-18 23:47:58 +00:00
Alyssa Rosenzweig 81d22da6de asahi: Fix BIND_PIPELINE sizing and alignment
Fix a bug in BIND_PIPELINE XML reported by Dougall, which cleans up
a bit of both decoder and driver.

Instead of...

   * 17 bytes BIND_PIPELINE  (17)
   * An unused 8 byte record (25)
   * A set of N 8 byte records (25 + 8 * N)
   * Oops, 1 byte too many! One just disappeared (24 + 8 * N)

It seems to instead be

   * 24 bytes BIND_PIPELINE (24)
   * A set of N 8 byte records (24 + 8 * N)

without the sentinel record. These means the 8 byte records themselves
are shuffled, with the high byte of the pointers split from the low
word, but that's less gross than an off-by-one.

It's still not clear what the last 8 bytes of the BIND_VERTEX_PIPELINE
structure mean, or the last 4 byte of the BIND_FRAGMENT_PIPELINE
structure which seems to be a bit shorter.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig 3b108393a2 asahi: Remove obnoxious workaround
Now that we're not hardcoded any magic BO IDs, there is no minimum
number of allocations needed. Remove the unneeded -- and obnoxious --
workaround of allocating unused BOs on startup.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig a28775046c asahi: Remove silly magic numbers
These are unnecessary now that the structure of agx_map_* is better
understood.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig d55a1a77bd asahi: Fix agx_map_* structures
Dougall Johnson observed these structures make more sense with indices[]
first in the entries and indices[] absent from the header. Then the
sentinel entry disappears, nr_entries makes more sense, and a few magic
numbers pop out. Many thanks to Dougall's astute eyes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig 6637fbb211 asahi: Allocate special scratch buffers
Seem to be used for preemption.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig 30433ae716 asahi: Deflake addresses
Reported by Dougall.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig df1824046a asahi: Rename PANDECODE->AGXDECODE
Fix remnant of the Panfrost decoder fork.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
2021-11-18 23:35:25 +00:00
Alyssa Rosenzweig e346ca5b41 pan/bi: Add XML for LD_BUFFER
Encoded like LOAD.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig 69ddbc4341 pan/bi: Suppress uniform validation for LD_BUFFER
Seems to be ok and used by the DDK...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig 36486f54e9 pan/bi: Confirm IDP unit on Valhall
Based on Anandtech which gives 8-bit dot product throughput on Valhall
under FMA and not consistent with SFU.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig b8ba909ca6 pan/bi: Forbid unaligned staging registers on Valhall
Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig df807cb839 pan/bi: Add XML for assembling Valhall image stores
Not complete yet but let's get some tests in early. Document the new
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig 58b65a340c pan/bi: Add Valhall's special FMA_RSCALE instructions
Like Bifrost, but exposed as separate physical instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig aee819d54c pan/bi: Add sqrt form of Valhall FREXPM
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00
Alyssa Rosenzweig 137053c4f4 pan/bi: Add full form of Valhall MUX instruction
Like Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
2021-11-18 23:16:20 +00:00