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pan/bi: Add XML for assembling Valhall image stores 

Not complete yet but let's get some tests in early. Document the new
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
This commit is contained in:
Alyssa Rosenzweig 2021-11-03 20:22:26 -04:00 committed by Marge Bot
parent 58b65a340c
commit df807cb839
2 changed files with 51 additions and 8 deletions
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53
src/panfrost/bifrost/valhall/ISA.xml
View File

@ -477,10 +477,10 @@
<reserved/>
<value desc="32-bit floats">f32</value>
<value desc="16-bit floats">f16</value>
<value desc="32-bit signed integers">s32</value>
<value desc="16-bit signed integers">s16</value>
<value desc="32-bit unsigned integers">u32</value>
<reserved/>
<reserved/>
<reserved/>
<value desc="16-bit unsigned integers">u16</value>
</enum>
<enum name="Staging register count" implied="true">
@ -719,12 +719,35 @@
<imm name="index" start="20" size="4"/>
</ins>
<ins name="LD_ATTR" title="Load indirect attribute" opcode="0x67" unit="LS">
<ins name="LEA_IMAGE_IMM" title="Load effective address of image texel" opcode="0x67" unit="LS">
<desc>
Load the effective address of a texel from the image specified with the
given immediate index. Returns three staging register: the low/high
32-bits of the address and the internal conversion descriptor. The format
of the internal conversion descriptor is compatible with Bifrost but
omits the register format, as this is specified with the ST_CVT
instruction on Valhall.
Coordinates are specified as 16-bit integers, packed into 32-bit sources.
</desc>
<vecsize/>
<slot/>
<sr_count/>
<sr write="true"/>
<imm name="unk" start="36" size="4"/>
<src>X/Y coordinates (16:16)</src>
<src>Z/W coordinates (16:16)</src>
<imm name="index" start="20" size="4"/>
<imm name="unk2" start="16" size="4"/>
</ins>
<ins name="LD_ATTR" title="Load indirect attribute" opcode="0x76" unit="LS">
<!-- TODO: for some reason, blob is using index (1<<24)|x for [x] -->
<desc>The index must not diverge within a warp.</desc>
<sr_count/>
<vecsize/>
<regfmt/>
<slot/>
<sr_count/>
<sr write="true"/>
<src>Vertex ID</src>
<src>Instance ID</src>
@ -856,12 +879,26 @@
<imm name="offset" start="8" size="16" signed="true"/>
</group>
<ins name="ST_IMAGE" title="Image store" opcode="0x71" unit="LS">
<desc>Stores to images</desc>
<ins name="ST_CVT" title="Store with conversion" opcode="0x71" unit="LS">
<desc>
Store to memory with data conversion. The address to store to is given in
the first source, which must be a 64-bit register (a pair of 32-bit
registers). For backwards compatibility with Bifrost, there is a second
source which should be the high 32-bits of the register. However, on
Valhall the first source is 64-bit so the second source is unused. The
third source is the conversion descriptor used for the store.
Used with LEA_IMAGE_IMM to implement image stores.
</desc>
<sr read="true"/>
<sr_count/>
<vecsize/>
<regfmt/>
<slot/>
<src>Address to store to after adding offset</src>
<src>64-bit address to store to (low)</src>
<src>64-bit address to store to (high)</src>
<src>Internal conversion descriptor</src>
<imm name="unk" start="36" size="4"/>
</ins>
<ins name="LD_TILE" title="Load from tilebuffer" opcode="0x78" unit="NONE">

6
src/panfrost/bifrost/valhall/test/assembler-cases.txt
View File

@ -106,3 +106,9 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
04 00 00 00 00 c7 91 08 MOV.i32.wait0 r7, r4
42 00 00 38 08 44 61 00 STORE.i128.slot0 @r4:r5:r6:r7, `r2, offset:0
41 f8 ff ff 07 c0 1f 50 BRANCHZ.reconverge `r1, offset:-8
7d c0 00 08 10 bc a1 00 IADD.v2u16 r60.h1, `r61.h10, 0x0
44 00 46 32 28 40 71 78 ST_CVT.v4.f32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 34 28 40 71 78 ST_CVT.v4.s32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 36 28 40 71 78 ST_CVT.v4.u32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
7c c0 12 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x1, unk2:0x2
7c c0 02 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x0, unk2:0x2