s_cmovk_i32 isn't GFX8_GFX9 only and s_version doesn't need a comment to say
it's GFX10+ exclusive. The encoding list is enough to provide this information,
as for other GFX10+ instructions.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16006>
If we change the sate without flushing the bitmap cache, the cache might be
rendered with the new scissor, which excludes some parts that should've
been rendered with the old state, and vice versa.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6233
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15881>
Here we just make sure we match the interpolation type on both
sides of the shader interface. Drivers like d3d12 are expecting
this.
Fixes: 9401990e6f ("nir/linker: set varying from uniform as flat")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16003>
Fix invalid usage of meson objects which violates official meson
specification and thus breaks muon, an implementation of meson
written in C.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15715>
This is used to determine the geometry shader info on GFX9, and it
looks like it was broken for topologies that use adjacency.
This is also used to remove PSIZ from shaders that don't need it.
Found by inspection.
fossils-db (Polaris10):
Totals from 140 (0.10% of 135960) affected shaders:
SGPRs: 10448 -> 9696 (-7.20%)
VGPRs: 4376 -> 4264 (-2.56%)
CodeSize: 164316 -> 161028 (-2.00%)
Instrs: 26449 -> 25767 (-2.58%)
Latency: 184448 -> 180468 (-2.16%)
InvThroughput: 80772 -> 79092 (-2.08%)
VClause: 337 -> 328 (-2.67%); split: -2.97%, +0.30%
SClause: 859 -> 813 (-5.36%); split: -5.70%, +0.35%
Copies: 1027 -> 790 (-23.08%)
PreSGPRs: 2751 -> 2331 (-15.27%)
PreVGPRs: 3887 -> 3836 (-1.31%)
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15948>
For example the SSO program may consist of just tcs -> gs or even
just a vs. In these cases we want to vectorise the externally
facing shader interfaces just like we would in non SSO programs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15941>
Fixes a hang on Gfx9 GT1 : dEQP-VK.compute.zero_initialize_workgroup_memory.max_workgroup_memory.128
Tested-by: Mark Janes <markjanes@swizzler.org>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596>
it's used by 3 different drivers, so it shouldn't be in radeonsi
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15907>
It's quite likely that the source of the f2i32 was already an integer, in
which case we can skip the ftrunc (particularly useful on the int-to-float
class of hardware that's unlikely to just have a native trunc opcode!).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15870>
Just like the other make-the-float-an-integer opcodes. Noticed in a
gallium nine shader run through TGSI-to-NIR, where the array index had
been floored by the user, but got implicitly rounded by DX9 array
indexing.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15870>
When we put NIR in the compiler stack for r300, indirect addressing broke
for gallium nine. DX's array indirects round the float value, so the DX
shader gets mapped to a TGSI "ARR ADDR[0] src.x" instruction. Translating
that to NIR maps to r0[f2i32(fround(src.x))]. While we might hope that in
translation back using nir-to-tgsi after optimization we would recognize
the construct and emit ARR again, that's going to be error prone (think
"what if src.x is in a NIR register?") so we need a fallback plan. r300
will be able to handle this lowering, so get it in place first to fix the
regression.
Fixes: #6297
Fixes: 7d2ea9b0ed ("r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15870>
Commit af1ee8e010 dropped support to
wl_drm, as we thought that most compositors from active projects were
already supporting zwp_linux_dmabuf_v1.
But that's not true, so revert this commit in order to give these
projects a longer transition period.
Note that we didn't add back the support to GEM name API, and that was
on purpose.
Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15822>
Document how to build and use Panfrost's drm-shim implementation. I hope by
documenting this process, other Mesa developers are better able to test
Panfrost. In particular, this allows developers without Mali hardware to run
shader-db for any Mali target, which may be useful for debugging regressions
from common NIR changes.
drm-shim is not a substitute for testing against real hardware.
Special thanks to Emma Anholt and Icecream95 for building this infrastructure.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15930>
Originally, PAN_GPU_ID was checked in the driver itself. I added the mechanism
to run Bifrost shader-db on my Midgard laptop. There was no drm-shim support at
this point, and this was a reasonable stop gap at the time.
Nowadays, we have a competent drm-shim implementation, which wholly replaces
this use case. So PAN_GPU_ID is only useful for drm-shim. Let's pull the code
into drm-shim and get it out of the driver. This allows NDEBUG drm-shim builds
to work properly.
While we're at it, the default emulated GPU is changed from Mali-T860 to
Mali-G52. This reflects our shifting development priorities.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15930>
Since 5d187e9cad ("panfrost: Add helpers to set batch masks"), we have common
helpers to set the colour and depth/stencil batch masks. Rather than set the
masks in various Midgard/Bifrost specific paths, set them generically based on
the finer dirty tracking. This lets us share the logic with Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15956>
Midgard aggregates a large amount of state into its renderer state descriptor.
Our current dirty tracking reflects this, with a single RENDERER dirty flag.
That won't work well on Valhall, which splits out orthogonal state into
independent descriptors (a blend descriptor, a depth/stencil descriptor, and so
on). To prepare for Valhall support, this patch moves the driver to finer dirty
tracking.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15956>
The optimized routine documented the tiling format together with the software
algorithm. The reference implementation wants the tiling format alone
documented. Let's break out the high level documentation into somewhere
centrally accessible, and refocus the comments in the optimized file on the
optimization.
This documentation is linked bidirectionally with both implementations, so it
should be easy to find.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
These are complex and not used in all dEQP paths. They're also easy to unit
test, so add some tests to prevent regressions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
The exact semantics of these routines are subtle, although they match what
Gallium wants. We're about to add unit tests. Add some comments that make it
obvious what it is we expect these routines to do. (In particular, it's not a
general region-of-interest copy, it's a region-of-interest of the tiled image
and the entire linear staging image.)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
We depend on this invariant implicitly. Make that dependence explicit so we
don't get confused and add broken unit tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
Now that tiled access to 3D textures works, we can enable tiling on all texture
targets. In particular, this adds tiling support for cube maps, arrays, and 3D
textures. Previously, these would usually fall back to linear, which is hard on
the caches.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
The tiled->linear conversion mechanism is meant for 2D and doesn't handle tiled
+ 3D. This use case is not expected application behaviour, it's not worth the
complexity to try to handle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
Thanks to our macros and some type trickery, our generic tiling routines are
type-generic. So we just need to add 48-bit and 96-bit texel types to tile. Note
we only support power-of-two bit sizes in the specialized tile routines for the
sake of replacing a multiplication with a shift.
With this change, all pixel formats supported in Panfrost are tileable.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15803>
Our I/O lowering doesn't handle 64-bit TCS stores and TES loads which use
several slots. Because of the large stride between slots, we have to split
the load so that there's a single load_buffer_amd/store_buffer_amd
intrinsic for each slot.
Our I/O lowering also sometimes creates nir_op_pack_64_2x32 after
nir_lower_alu_to_scalar.
Fixes KHR-GL45.gpu_shader_fp64.fp64.varyings with Zink
(https://gitlab.freedesktop.org/mesa/mesa/-/issues/6276)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15863>
This fixes a number of tests like :
dEQP-VK.renderpass*.suballocation.multisample.s8_uint.*
dEQP-VK.renderpass*.suballocation.multisample.separate_stencil_usage.d24_unorm_s8_uint.*.test_stencil
dEQP-VK.renderpass*.suballocation.multisample.d24_unorm_s8_uint.*
dEQP-VK.renderpass*.suballocation.multisample.d32_sfloat_s8_uint.*
Because the driver asserts when generating RENDER_SURFACE_STATE with a
8 Valign value for stencil buffer (only 2 & 4 are supported).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12670>
With VK_EXT_graphics_pipeline_library, modules can be passed via the
pNext of VkpipelineShaderStageCreateInfo.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15926>
Konstantin Seurer
Georg Lehmann
Sviatoslav Peleshko
Juan A. Suarez Romero
Timothy Arceri
illiliti
Samuel Pitoiset
Lionel Landwerlin
Josh Billingsley
Gert Wollny
Marek Olšák
Emma Anholt
Leandro Ribeiro
Icecream95
Alyssa Rosenzweig
Rhys Perry
Michel Zou
Jason Ekstrand