Commit Graph

900 Commits

Author SHA1 Message Date
Marek Olšák 25cdf754e4 radeonsi: remove some old gfx 9.x registers
Leftover from bring up.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:56 -04:00
Marek Olšák 8c1c451a90 ac/surface/gfx6: don't overallocate mipmapped HTILE
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-24 13:41:56 -04:00
Bas Nieuwenhuizen 699e1f5aac ac: Use DPP for build_ddxy where possible.
WQM is pretty reliable now on LLVM 7, so let us just use
DPP + WQM.

This gives approximately a 1.5% performance increase on the
vrcompositor built-in benchmark.

v2: Use ac_build_quad_swizzle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-23 21:02:45 +02:00
Bas Nieuwenhuizen 047438287c ac/surface/gfx6: Don't force a tile index for fmask.
The bpe of the fmask often differs from the bpe of the main
surface. On SI that means it has to get a different tile
index.

addrlib is capable of figuring this out itself, so just pass
-1 instead to let it know that it is not preset.

Fixes: 9bf3570fed "ac/surface/gfx6: compute FMASK together with the color surface"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106511
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106499
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-05-23 02:23:03 +02:00
Bas Nieuwenhuizen a1c87235a9 ac/surface: Only align linear power of two fmt textures.
We're not sharing 32_32_32 formats between different GPUs, so we
do not have to align for vega on pre-vega cards.

Fixes: e361970ed7 "radv: Add support for IMG_DATA_FORMAT_32_32_32."
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-05-20 11:57:59 +02:00
Marek Olšák f9eb1ef870 amd: remove support for LLVM 4.0
It doesn't support GFX9.

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-17 14:54:41 -04:00
Dave Airlie eba4cf797c ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic
Drop the use of the old intrinsic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-05-17 11:46:53 +10:00
Bas Nieuwenhuizen e361970ed7 radv: Add support for IMG_DATA_FORMAT_32_32_32.
Basic sampling support for linear tiling.

No CTS regressions, but it seems the blitting coverage is not very
extensive.

https://bugs.freedesktop.org/show_bug.cgi?id=106331
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-14 18:58:12 +02:00
Bas Nieuwenhuizen dd102405de radv: Translate logic ops.
radeonsi could pass them through but the enum changed between
Gallium and Vulkan, so we have to translate.

In progress I made the register defines a bit more readable.

CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-14 16:49:06 +02:00
Marek Olšák a2e9d9b4c1 ac/gpu_info: add has_read_registers_query
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:11 -04:00
Marek Olšák 9b1fdfc541 ac/gpu_info: add has_2d_tiling
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:10 -04:00
Marek Olšák d26696283d ac/gpu_info: add has_sparse_vm_mappings
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:08 -04:00
Marek Olšák 125adc92ad ac/gpu_info: add has_unaligned_shader_loads
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:07 -04:00
Marek Olšák e9c08bc658 ac/gpu_info: add has_indirect_compute_dispatch
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:03 -04:00
Marek Olšák 64265ac8d5 ac/gpu_info: add kernel_flushes_tc_l2_after_ib
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:01 -04:00
Marek Olšák 14c5a93bfa ac/gpu_info: add has_format_bc1_through_bc7
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:40:00 -04:00
Marek Olšák 2bd2c173e8 ac/gpu_info: add has_eqaa_surface_allocator
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:58 -04:00
Marek Olšák e720cb6135 radeonsi: clean up the reset status query implementation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:57 -04:00
Marek Olšák 3060f62340 ac/gpu_info: add has_bo_metadata
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:56 -04:00
Marek Olšák 09f1bab483 ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:54 -04:00
Marek Olšák 8b58a14ef7 ac/gpu_info: add htile_cmask_support_1d_tiling
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:53 -04:00
Marek Olšák b81149e258 ac/gpu_info: add kernel_flushes_hdp_before_ib
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:39:47 -04:00
Marek Olšák 912b0163dc ac/surface: add EQAA support
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:34:31 -04:00
Marek Olšák bdc3e410f7 ac/surface: unify common legacy and gfx9 fmask fields
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:33 -04:00
Marek Olšák 9bf3570fed ac/surface/gfx6: compute FMASK together with the color surface
instead of invoking FMASK computation separately.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:33 -04:00
Marek Olšák 276acda835 ac/surface/gfx9: fix a typo in CMASK RB/pipe alignment
No change in behavior because it's always aligned.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Marek Olšák 6841845b00 ac: set correct LLVM processor names for Raven & Vega12
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Marek Olšák 6f7f10d285 ac: sort raster configs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Marek Olšák e7b82a9978 ac: remove 1 RB raster config for Iceland
Iceland always reports 2 RBs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Marek Olšák cb0f5cddcc ac: move the Fiji kernel workaround for raster config out of the switch
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Marek Olšák ce954ac6f3 ac: enable both RBs on Kaveri
This can result in 2x increase in performance on non-harvested Kaveris.

v2: don't do it on radeon

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-05-10 18:26:32 -04:00
Nicolai Hähnle c0acb596f4 amd/common: use llvm.amdgcn.wqm for explicit derivatives
To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-04 11:02:48 +02:00
Dave Airlie 8d3529872c ac/nir: expand 64-bit vec3 loads to fix shuffling.
If loading 64-bit vec3 values, a 4 component load would be followed
by a 2 component load and the resulting shuffle would fail as it
requires 2 4 components. This just expands the second results
vector out to 4 components.

This fixes 100 CTS tests:
dEQP-VK.spirv_assembly.type.vec3.*64*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-01 05:58:14 +10:00
Marek Olšák 43f0a10051 radeonsi: add triple into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák 174e11c3f5 ac/surface: handle DCC subresource fast clear restriction on VI
v2: require the previous level to be clearable for determining whether
    the last unaligned level is clearable

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Samuel Pitoiset d38425ce87 ac: fix texture query LOD for 1D textures on GFX9
1D textures are allocated as 2D which means we only need
one coordinate for texture query LOD.

Fixes: 625dcbbc45 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 11:15:35 +02:00
Dave Airlie a90c9f33cf ac/radv/radeonsi: refactor harvest config register getters.
This refactors the code out to share it between radv and radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-24 09:08:34 +10:00
Dave Airlie f77caa7411 ac/radv/radeonsi: refactor max simd waves into common code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-24 09:08:33 +10:00
Dave Airlie 899df55ee0 ac/radv/radeonsi: refactor raster_config default values getters.
This just makes this common code between the two drivers.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-24 09:07:51 +10:00
Dave Airlie 5e2ef28390 ac/info: move gs table depth to common code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-24 09:05:38 +10:00
Samuel Pitoiset d136a5fad9 ac: fix the number of coordinates for ac_image_get_lod and arrays
This fixes crashes for the following CTS:
dEQP-VK.glsl.texture_functions.query.texturequerylod.*

Cubemaps are the same as 2D arrays.

Fixes: 625dcbbc45 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-23 21:48:38 +02:00
Samuel Pitoiset e37e643589 ac: teach get_ac_sampler_dim() about subpass attachments
Suggested by Nicolai.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-23 19:10:56 +02:00
Samuel Pitoiset 84fef802fb ac/nir: add missing round_slice for 1D arrays
This fixes a bunch of CTS fails with 1D arrays:

dEQP-VK.glsl.texture_functions.texture*.sampler1darray_*

Fixes: 625dcbbc45 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-23 19:10:52 +02:00
Samuel Pitoiset 8f13975713 ac/nir: fix image dimension for subpass attachments
For subpass attachments we need one more coordinate with
the layer, so make them array types.

This fixes a bunch of CTS fails with RADV.

Fixes: 24fb3e6aa1 ("ac/nir: use ac_build_image_opcode for image intrinsics")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-20 18:44:51 +02:00
Samuel Pitoiset dd069e9b41 ac/nir: handle nir_intrinsic_load_first_vertex like base_vertex
This fixes a ton of CTS crashes.

Fixes: c366f422f0 ("nir: Offset vertex_id by first_vertex instead of base_vertex")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-20 17:07:38 +02:00
Nicolai Hähnle 24fb3e6aa1 ac/nir: use ac_build_image_opcode for image intrinsics
So that we'll use the dimension-aware intrinsics in the future.

Acked-by: Marek Olšák <marek.olsak@amd.com>
2018-04-20 09:30:07 +02:00
Nicolai Hähnle 74063431f1 radeonsi: generate image load/store/atomic ops using ac_build_image_opcode
In preparation of dimension-aware LLVM image intrinsics.

Acked-by: Marek Olšák <marek.olsak@amd.com>
2018-04-20 09:29:57 +02:00
Nicolai Hähnle 625dcbbc45 amd/common: pass address components individually to ac_build_image_intrinsic
This is in preparation for the new image intrinsics.

Acked-by: Marek Olšák <marek.olsak@amd.com>
2018-04-20 09:23:52 +02:00
Nicolai Hähnle f931583828 amd/common: pass new enum ac_image_dim to ac_build_image_opcode
This is in preparation for the new, dimension-aware LLVM image
intrinsics.

Acked-by: Marek Olšák <marek.olsak@amd.com>
2018-04-20 09:23:40 +02:00
Nicolai Hähnle a807a9b215 ac/nir: fix atomic compare-and-swap
The LLVM instruction returns { i32, i1 }, where the i1 indicates success.
We're only interested in the first part, which is the loaded value.

Fixes dEQP-GLES31.functional.compute.shared_var.atomic.compswap.*

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-20 09:21:40 +02:00