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ac/gpu_info: add has_sparse_vm_mappings 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2018-05-02 19:48:37 -04:00
parent 125adc92ad
commit d26696283d
4 changed files with 12 additions and 11 deletions
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8
src/amd/common/ac_gpu_info.c
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@ -330,6 +330,13 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_indirect_compute_dispatch = true;
/* SI doesn't support unaligned loads. */
info->has_unaligned_shader_loads = info->chip_class != SI;
/* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
* these faults are mitigated in software.
* Disable sparse mappings on GFX9 due to hangs.
*/
info->has_sparse_vm_mappings =
info->chip_class >= CIK && info->chip_class <= VI &&
info->drm_minor >= 13;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@ -488,6 +495,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);

1
src/amd/common/ac_gpu_info.h
View File

@ -107,6 +107,7 @@ struct radeon_info {
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */

13
src/gallium/drivers/radeonsi/si_get.c
View File

@ -229,17 +229,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
/* TODO: GFX9 hangs. */
if (sscreen->info.chip_class >= GFX9)
return 0;
/* Disable on SI due to VM faults in CP DMA. Enable once these
* faults are mitigated in software.
*/
if (sscreen->info.chip_class >= CIK &&
sscreen->info.drm_major == 3 &&
sscreen->info.drm_minor >= 13)
return RADEON_SPARSE_PAGE_SIZE;
return 0;
return sscreen->info.has_sparse_vm_mappings ?
RADEON_SPARSE_PAGE_SIZE : 0;
case PIPE_CAP_PACKED_UNIFORMS:
if (sscreen->debug_flags & DBG(NIR))

1
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@ -547,6 +547,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* SI doesn't support unaligned loads. */
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
ws->info.drm_minor >= 50;
ws->info.has_sparse_vm_mappings = false;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;