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i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE 

According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.

gen3 BSpec no longer has that piece of text, but let's make the same
change there too for symmetry. The spec does still say that the scissor
rectangle must be defined before enabling it, so the new order does seem
more in line with the spec.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Ville Syrjälä 2014-07-06 15:02:15 +03:00
parent 81c31e560f
commit 0d924738d9
6 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mesa/drivers/dri/i915/i830_context.h
View File

@ -55,10 +55,10 @@
#define I830_DESTREG_DBUFADDR1 3
#define I830_DESTREG_DV0 4
#define I830_DESTREG_DV1 5
#define I830_DESTREG_SENABLE 6
#define I830_DESTREG_SR0 7
#define I830_DESTREG_SR1 8
#define I830_DESTREG_SR2 9
#define I830_DESTREG_SR0 6
#define I830_DESTREG_SR1 7
#define I830_DESTREG_SR2 8
#define I830_DESTREG_SENABLE 9
#define I830_DESTREG_DRAWRECT0 10
#define I830_DESTREG_DRAWRECT1 11
#define I830_DESTREG_DRAWRECT2 12

4
src/mesa/drivers/dri/i915/i830_state.c
View File

@ -1069,11 +1069,11 @@ i830_init_packets(struct i830_context *i830)
i830->state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;
i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i830->state.Buffer[I830_DESTREG_SR1] = 0;
i830->state.Buffer[I830_DESTREG_SR2] = 0;
i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
}
void

2
src/mesa/drivers/dri/i915/i830_vtbl.c
View File

@ -510,10 +510,10 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);

8
src/mesa/drivers/dri/i915/i915_context.h
View File

@ -64,10 +64,10 @@
#define I915_DESTREG_DBUFADDR1 4
#define I915_DESTREG_DV0 6
#define I915_DESTREG_DV1 7
#define I915_DESTREG_SENABLE 8
#define I915_DESTREG_SR0 9
#define I915_DESTREG_SR1 10
#define I915_DESTREG_SR2 11
#define I915_DESTREG_SR0 8
#define I915_DESTREG_SR1 9
#define I915_DESTREG_SR2 10
#define I915_DESTREG_SENABLE 11
#define I915_DESTREG_DRAWRECT0 12
#define I915_DESTREG_DRAWRECT1 13
#define I915_DESTREG_DRAWRECT2 14

4
src/mesa/drivers/dri/i915/i915_state.c
View File

@ -980,11 +980,11 @@ i915_init_packets(struct i915_context *i915)
i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
/* scissor */
i915->state.Buffer[I915_DESTREG_SENABLE] =
(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i915->state.Buffer[I915_DESTREG_SR1] = 0;
i915->state.Buffer[I915_DESTREG_SR2] = 0;
i915->state.Buffer[I915_DESTREG_SENABLE] =
(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
}
i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |

8
src/mesa/drivers/dri/i915/i915_vtbl.c
View File

@ -206,13 +206,13 @@ i915_emit_invarient_state(struct intel_context *intel)
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
@ -415,10 +415,10 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);