Commit Graph

156168 Commits

Author SHA1 Message Date
Martin Roukala (né Peres) acbec0fa23 radv/ci: allow specifying a warning pattern
This will be used to detect soft resets without aborting the run, but
still make the job fail.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>
2022-07-02 13:06:49 +03:00
Samuel Pitoiset 3e90eb4463 radv/ci: add CI lists for LLVM on NAVI21
Copied and adjusted from the ACO lists.

v2: Martin Roukala
 - add an extra test in the list of timeouts
 - add an extra test in the list of flakes
 - remove a fail

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>
2022-07-02 13:06:49 +03:00
Martin Roukala (né Peres) c0fbc31737 radv/ci: test the llvm backend on navi21
The LLVM backend is not officially supported by the RADV developers,
but it has been useful early during bring-up, or later when users are
experiencing what looks like a compiler bug. It is thus beneficial to
keep it working.

However, maintaining the vkcts expectations for every platform requires
more work and machine time than what we would like to commit to. This
is why we agreed that we would only keep LLVM tested on the latest
family of Radeon GPUs.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>
2022-07-02 12:35:51 +03:00
Jesse Natalie a0c2b34248 gallium/util: Move u_dl and u_pointer to src/util
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17327>
2022-07-01 21:15:07 +00:00
Christian Gmeiner 1141ed5859 etnaviv: async shader compile
Passes following piglit:
 - spec@khr_parallel_shader_compile@basic

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16172>
2022-07-01 19:55:36 +00:00
Christian Gmeiner a427a7f5d4 etnaviv: factor out shader screen related init/deint
This is a prep step for the next changes.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16172>
2022-07-01 19:55:36 +00:00
Martin Roukala (né Peres) 4d7c11aa8d ci/x86: update to llvm 13
Most CI tests are currently running on LLVM 11 (released over 2 years
ago), which predates some of the GPUs we have in CI and prevents
testing RADV's LLVM backend.

LLVM 13 is known to work for RADV, released almost 8 months ago, and
is already available in most distributions. Fedora 36 is even already
on LLVM 14.

So this commit updates x86 testing on llvm 13.

v2:
 - store the llvm apt repo key locally (Michel Dänzer)

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17188>
2022-07-01 19:24:05 +00:00
Timur Kristóf ff13fc381d radv: Use NIR optimization to move discards to the top.
Fossil stats on Sienna Cichlid:

Totals from 1988 (1.55% of 128653) affected shaders:
VGPRs: 68096 -> 67928 (-0.25%); split: -0.61%, +0.36%
CodeSize: 5391936 -> 5391312 (-0.01%); split: -0.11%, +0.10%
MaxWaves: 53020 -> 52946 (-0.14%); split: +0.05%, -0.19%
Instrs: 992413 -> 992509 (+0.01%); split: -0.10%, +0.11%
Latency: 8643141 -> 8789295 (+1.69%); split: -0.31%, +2.00%
InvThroughput: 1680195 -> 1680605 (+0.02%); split: -0.04%, +0.07%
SClause: 50886 -> 51318 (+0.85%); split: -0.73%, +1.57%
Copies: 57017 -> 56741 (-0.48%); split: -1.28%, +0.80%
PreSGPRs: 66766 -> 67048 (+0.42%); split: -0.24%, +0.66%
PreVGPRs: 56832 -> 56935 (+0.18%); split: -0.44%, +0.62%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13037>
2022-07-01 18:55:53 +00:00
Yiwei Zhang 1b4784c5fb venus: swizzle the chroma channels for YVU420 to match the VkFormat
Test:
- testVP8EncodeDecodeVideoFromBufferToSurface
- android.media.cts.DecodeAccuracyTest

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17323>
2022-07-01 18:46:31 +00:00
Timur Kristóf 5d2a243dde radv: Add CULL_PRIMITIVE to special output mask.
It isn't compiled to an output param, so can be safely ignored
from the param assignment.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Timur Kristóf 7144d52d59 radv: Don't assign driver locations to mesh shader outputs.
Set all driver locations to zero.
These are ignored by ac_nir_lower_ngg anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Timur Kristóf 8bfeb467bf ac/nir/ngg: Ignore driver location for mesh shader outputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Martin Roukala (né Peres) 66bd470922 ci/radv: enable vkcts testing on kabini
It seems like the hangs have been resolved on kabini, so let's allow
developers to run their tests on kabini, if they are *very* patient
(~10h).

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17129>
2022-07-01 16:44:14 +00:00
David Heidelberg 1bcb883ea5 ci/freedreno: disable SpecOps trace, each run flaky
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17336>
2022-07-01 15:47:09 +00:00
Jonathan Marek de8c769d11 freedreno/registers: add a7xx registers for drm/msm kernel driver
Most of this is taken directly from the downstream kernel driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602>
2022-07-01 15:11:28 +00:00
Jesse Natalie 31fab141df dzn: Support Vulkan loader interface v5
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17321>
2022-07-01 14:56:18 +00:00
Konstantin Seurer 6a90d3832a radv: Use two bools for ahit_status
This avoids using a VGPR and uses two SGPRs
instead since we only need to store 2 bits.

Quake II RTX:

Totals from 7 (0.46% of 1513) affected shaders:
CodeSize: 229364 -> 229148 (-0.09%); split: -0.12%, +0.02%
Instrs: 41937 -> 41879 (-0.14%)
Latency: 977374 -> 976723 (-0.07%)
InvThroughput: 651582 -> 651148 (-0.07%)
Copies: 5064 -> 5033 (-0.61%)
PreSGPRs: 430 -> 433 (+0.70%)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17293>
2022-07-01 14:31:49 +00:00
David Heidelberg 6f2a991f78 ci/freedreno: disable Stellaris trace
Revert when it gets fixed on CI runner (works on OnePlus 6T with
5.18 kernel).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg f77695d13f ci/freedreno: temporary disable AmnesiaTDD
Revert when https://gitlab.freedesktop.org/mesa/mesa/-/issues/6763 get fixed.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg 74da4dc216 ci/freedreno: add more restricted traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:03 +02:00
Daniel Schürmann 862f1eacb2 nir/opt_shrink_vectors: fix re-using of components for vecN
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17276>
2022-07-01 12:01:21 +00:00
Danylo Piliaiev c655387a02 ir3: Use NIR's info.writes_memory to detect when when to force late-z
Better than maintaining our old checks.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16818>
2022-07-01 11:37:17 +00:00
Iago Toral Quiroga 7b91b39ba5 v3dv: fix pool descriptor count for inline uniform buffers
Fixes VK_ERROR_OUT_OF_POOL_MEMORY in the inlineuniformblocks
sample from Sascha Willems.

Fixes: ea3223e7a4 ('v3dv: implement VK_EXT_inline_uniform_block')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17311>
2022-07-01 11:12:39 +00:00
Jordan Justen d5884a716f vulkan/wsi: Disable dma-buf sync file if ENOSYS is returned
ENOSYS is commented as "Invalid system call number". This is returned
by qemu-user for unbridged ioctls.

Fixes: 30b57f10b3 ("vulkan/wsi: Signal semaphores and fences from the dma-buf")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17325>
2022-07-01 10:28:34 +00:00
Boris Brezillon a577acf8f6 dzn: Mark transition barriers as executed when we execute barriers
It was previously done dzn_cmd_buffer_flush_transition_barriers(),
leaving the queue+flush case unhandled. Let's fix that by moving
this piece of code to dzn_cmd_buffer_exec_transition_barriers().

Fixes: 35356b1173 ("dzn: Cache and pack transition barriers")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17314>
2022-07-01 09:42:58 +00:00
Eric Engestrom c06926f694 broadcom/rpi4-skips: drop duplicated lines
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17312>
2022-07-01 08:09:48 +00:00
Timothy Arceri f533dfff55 glsl: drop non-nir path for atan in builtin functions
All drivers now use NIR. Here we drop the non NIR path and rename
the NIR path to drop the extra "_op" chars from the function names.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17308>
2022-07-01 03:05:03 +00:00
Kenneth Graunke 589b03d02f intel/fs: Opportunistically split SEND message payloads
While we've taken advantage of split-sends in select situations, there
are many other cases (such as sampler messages, framebuffer writes, and
URB writes) that have never received that treatment, and continued to
use monolithic send payloads.

This commit introduces a new optimization pass which detects SEND
messages with a single payload, finds an adjacent LOAD_PAYLOAD that
produces that payload, splits it two, and updates the SEND to use both
of the new smaller payloads.

In places where we manually used split SENDS, we rely on underlying
knowledge of the message to determine a natural split point.  For
example, header and data, or address and value.

In this pass, we instead infer a natural split point by looking at the
source registers.  Often times, consecutive LOAD_PAYLOAD sources may
already be grouped together in a contiguous block, such as a texture
coordinate.  Then, there is another bit of data, such as a LOD, that
may come from elsewhere.  We look for the point where the source list
switches VGRFs, and split it there.  (If there is a message header, we
choose to split there, as it will naturally come from elsewhere.)

This not only reduces the payload sizes, alleviating register pressure,
but it means that we may be able to eliminate some payload construction
altogether, if we have a contiguous block already and some extra data
being tacked on to one side or the other.

shader-db results for Icelake are:

   total instructions in shared programs: 19602513 -> 19369255 (-1.19%)
   instructions in affected programs: 6085404 -> 5852146 (-3.83%)
   helped: 23650 / HURT: 15
   helped stats (abs) min: 1 max: 1344 x̄: 9.87 x̃: 3
   helped stats (rel) min: 0.03% max: 35.71% x̄: 3.78% x̃: 2.15%
   HURT stats (abs)   min: 1 max: 44 x̄: 7.20 x̃: 2
   HURT stats (rel)   min: 1.04% max: 20.00% x̄: 4.13% x̃: 2.00%
   95% mean confidence interval for instructions value: -10.16 -9.55
   95% mean confidence interval for instructions %-change: -3.84% -3.72%
   Instructions are helped.

   total cycles in shared programs: 848180368 -> 842208063 (-0.70%)
   cycles in affected programs: 599931746 -> 593959441 (-1.00%)
   helped: 22114 / HURT: 13053
   helped stats (abs) min: 1 max: 482486 x̄: 580.94 x̃: 22
   helped stats (rel) min: <.01% max: 78.92% x̄: 4.76% x̃: 0.75%
   HURT stats (abs)   min: 1 max: 94022 x̄: 526.67 x̃: 22
   HURT stats (rel)   min: <.01% max: 188.99% x̄: 4.52% x̃: 0.61%
   95% mean confidence interval for cycles value: -222.87 -116.79
   95% mean confidence interval for cycles %-change: -1.44% -1.20%
   Cycles are helped.

   total spills in shared programs: 8387 -> 6569 (-21.68%)
   spills in affected programs: 5110 -> 3292 (-35.58%)
   helped: 359 / HURT: 3

   total fills in shared programs: 11833 -> 8218 (-30.55%)
   fills in affected programs: 8635 -> 5020 (-41.86%)
   helped: 358 / HURT: 3

   LOST:   1 SIMD16 shader, 659 SIMD32 shaders
   GAINED: 65 SIMD16 shaders, 959 SIMD32 shaders

   Total CPU time (seconds): 1505.48 -> 1474.08 (-2.09%)

Examining these results: the few shaders where spills/fills increased
were already spilling significantly, and were only slightly hurt.  The
applications affected were also helped in countless other shaders, and
other shaders stopped spilling altogether or had 50% reductions.  Many
SIMD16 shaders were gained, and overall we gain more SIMD32, though many
close to the register pressure line go back and forth.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>
2022-07-01 02:05:45 +00:00
Kenneth Graunke a8b93e628a intel/compiler: Handle split-sends in EOT high-register pinning case
SEND messages with EOT need to use g112-g127 for their sources so that
the hardware is able to launch new threads while old ones are finishing
without worrying about register overlap when pushing payloads.  For the
newer split-send messages, this applies to both source registers.

Our special case for this in the register allocator was only considering
the first source.  This wasn't a problem because we hadn't ever tried to
use split-sends with EOT before.  However, my new optimization pass is
going to introduce some shortly, so we'll need to handle them properly.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>
2022-07-01 02:05:45 +00:00
Dave Airlie 68642e2c26 aco: drop radv_shader.h include
This shouldn't be used anymore

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie 9fe2b6b748 aco/radv: provide a vs prolog callback from aco to radv.
Avoid building the radv binary in aco, just callback with the
necessary info.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie 2dce77c239 aco/radv: provide a callback from aco shader building to build binary
This moves the radv specific code into radv, and calls back from
aco into radv.

This should allow easier radeonsi integration later.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie e5ec50b3c7 aco: refactor the radv binary builder out of the core aco fn.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Kenneth Graunke dd76196cea intel/compiler: Convert brw_eu.cpp back to brw_eu.c
Now that we've removed the thread_local lookup tables using
pointer-to-member C++ features, this can go back to being a standard
C file, like it was in the past.  We just need to annotate a couple
of things with "struct".

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke ea72ec98bf intel/compiler: Remove use of thread_local for opcode tables
We had been using thread_local index -> opcode_desc tables to avoid
plumbing through a storage location throughout all the code.  But now
we have done so with the new brw_isa_info structure.  So we can just
store the tables there, and initialize it with the compiler.

This fixes crashes in gtk4-demo on iris, and should help with some
programs on zink as well.  Something was going wrong with the
thread_local variables not being set up correctly.  While we might be
able to work around that issue, there's really no advantage to storing
these lookup tables in TLS (beyond it being simpler to do originally).
So let's simply stop doing so.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6728
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6229
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke 72e9843991 intel/compiler: Introduce a new brw_isa_info structure
This structure will contain the opcode mapping tables in the next
commit.  For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke 342471e93d intel/compiler: Move opcode_desc handling to a separate header
This patch creates a new header file, brw_isa_info.h, which will
contains all the functions related to opcode encoding on various
generations.  Opcode numbers may have different meanings on different
hardware, so we remap them between an enum we can easily work with
and the hardware encoding.

We move the brw_inst setters and getters to brw_inst.h.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke c0784804a1 intel/tools: Stop malloc'ing device info in i965_disasm
There's not really any point, a stack allocated struct works fine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke fdae90aa85 intel/compiler: Split 3DPRIM_* defines out to a separate header.
These clash with genxml and will become a problem shortly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke 9f8784232a intel/compiler: Fix brw_gfx_ver_enum.h to be a proper header file
This header file didn't include normal guards against being included
multiple times.  It also defined a function in a header file without
marking it static inline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke a141a351de intel/compiler: Stop including src/mesa/main/config.h
src/mesa/main includes are for Mesa's OpenGL implementation, and the
compiler is used in Vulkan drivers and other tools.  We really only
needed one #define, which is that we offer 32 samplers.  It probably
makes more sense to have our own defined limit for that rather than
importing a project-wide value which theoretically could be adjusted,
so swap MAX_SAMPLERS for a new BRW_MAX_SAMPLERS and call it a day.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke 434bc468fe crocus: Use PIPE_* defines rather than ones from main/config.h
Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Kenneth Graunke 0ce9d7b7c9 iris: Use PIPE_* defines rather than ones from main/config.h
Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
2022-06-30 23:46:35 +00:00
Mike Blumenkrantz 90c5eea22b zink: enforce viewport depth clamping
VUID-VkViewport-minDepth-01234 specifies that depth must be in the range [0.0, 1.0],
so the viewport must always be clamped to this range

this affects texture clears using u_blitter, as this expects to be able
to use the GL range of [-1.0, 1.0], so pass the depth value as though it's
been de-converted back to a GL z coordinate to account for viewport transform

cc: mesa-stable

fixes #6757

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17319>
2022-06-30 22:57:10 +00:00
Mike Blumenkrantz 1334d39b36 lavapipe: don't remove xfb outputs
cc: mesa-stable

fixes:
dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
dEQP-VK.transform_feedback.simple.multiquery_omit_write_3
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_64bits

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17299>
2022-06-30 22:46:51 +00:00
Mike Blumenkrantz 6004293f19 zink: disable turnip traces temporarily
this needs a libX11 update

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17313>
2022-06-30 20:20:21 +00:00
Yiwei Zhang 9f59acaa48 venus: use narrow range to match up with mesa EGL
This matches up with the native gl drivers as well as the media stack.

Test: android.graphics.cts.MediaVulkanGpuTest
Test: android.media.cts.EncodeDecodeTest

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17306>
2022-06-30 20:11:04 +00:00
Rhys Perry 93fd97cec4 radv/ci: re-enable vega10 fossils testing
Should work now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>
2022-06-30 19:30:55 +00:00
Rhys Perry 84f04fd080 aco/ra: update register file when updating phi definition
update_renames() fills in the wrong temp id.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 302cb5c900 ("aco/ra: remove some redundant code")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>
2022-06-30 19:30:55 +00:00
Dylan Baker 4bcd753da4 docs: update calendar and link releases notes for 22.1.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>
2022-06-30 19:11:44 +00:00