Commit Graph

27 Commits

Author SHA1 Message Date
Michel Dänzer 313104e8d5 r600g/radeonsi: Use caching buffer manager for textures as well
Significantly reduces BO allocation / destruction overhead for transfers,
e.g. measurable via x11perf -shm{ge,pu}t* with glamor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-15 11:34:56 +09:00
Marek Olšák 4d641803e8 radeonsi: allow fast color clear and Hyper-Z with 1D-tiled surfaces on CIK
This depends on my kernel fix. Hyper-Z is still disabled by default.
2014-04-09 01:45:16 +02:00
Marek Olšák 4a5519f1e0 r600g,radeonsi: set correct initial domain for shared resources 2014-04-09 01:45:16 +02:00
Leo Liu 0817182b2f Revert "radeon: just don't map VRAM buffers at all"
This reverts commit 96e8b916a7.
In the case of VCE encoding with raw YUV file, CPU load directly
to VRAM is faster than combination of CPU writing to GTT and
then blit to VRAM with GPU.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-04 16:21:04 +02:00
Marek Olšák 011569b5b7 radeonsi: disable fast color clear for 1D-tiled surfaces on CIK
This will be re-enabled once my kernel fix lands.
2014-03-22 18:44:58 +01:00
Marek Olšák 4ca3486b19 r600g,radeonsi: use a fallback in dma_copy instead of failing
v2: - allow byte-aligned DMA buffer copies on Evergreen
    - fix piglit/texsubimage regression
    - use the fallback for 3D copies (depth > 1) as well
2014-03-11 19:18:02 +01:00
Marek Olšák a38e1fd78b radeonsi: implement fast color clear
This works for both multi-sample and single-sample color buffers.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-11 18:51:20 +01:00
Marek Olšák 28eb0bcf19 r600g: move fast color clear code to a common place
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-11 18:51:20 +01:00
Marek Olšák d3c1be530a r600g,radeonsi: move CMASK register values from r600_surface to r600_texture
When doing fast clear for single-sample color buffers for the first time,
a CMASK buffer has to be allocated and the CMASK state in all pipe_surfaces
referencing the color buffer must be updated. Updating all surfaces is kinda
silly, so let's move the values to r600_texture instead.

This is only for Evergreen and later. R600-R700 don't have fast clear.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-11 18:51:20 +01:00
Marek Olšák dff3eccd15 radeonsi: move translate_colorswap to common code
Also translate the Y__X swizzle.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-03-04 12:26:16 +01:00
Marek Olšák 9855477e90 r600g,radeonsi: consolidate create_surface and surface_destroy
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-02-25 16:08:26 +01:00
Alex Deucher 01e6371149 radeon: reverse DBG_NO_HYPERZ logic
Change the flag to DBG_HYPERZ and reverse the logic
so setting the flag enabled the feature.  This disables
hyperz on r600g and radeonsi by default.  It can be
enabled by setting the env var.  There are just too
many issues with certain apps so leave it disabled for
now until we sort out the issues with the problematic
apps.

Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=58660
https://bugs.freedesktop.org/show_bug.cgi?id=64471
https://bugs.freedesktop.org/show_bug.cgi?id=66352
https://bugs.freedesktop.org/show_bug.cgi?id=68799
https://bugs.freedesktop.org/show_bug.cgi?id=72685
https://bugs.freedesktop.org/show_bug.cgi?id=73088
https://bugs.freedesktop.org/show_bug.cgi?id=74428
https://bugs.freedesktop.org/show_bug.cgi?id=74803
https://bugs.freedesktop.org/show_bug.cgi?id=74863
https://bugs.freedesktop.org/show_bug.cgi?id=74892
https://bugzilla.kernel.org/show_bug.cgi?id=70411

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "10.1" "10.0" <mesa-stable@lists.freedesktop.org>
Acked-by: Marek Olšák <marek.olsak@amd.com>
2014-02-13 20:55:54 -05:00
Marek Olšák c32114460d gallium: remove PIPE_USAGE_STATIC
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-02-06 17:37:34 +01:00
Marek Olšák 2be5bbdd97 r600g,radeonsi: set resource domains in one place (v2)
v2: This doesn't change the behavior. It only moves the tiling check
    to r600_init_resource and removes the usage parameter.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-02-06 17:29:59 +01:00
Christian König 96e8b916a7 radeon: just don't map VRAM buffers at all
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-02-06 16:08:22 +01:00
Marek Olšák a9ae7635b7 r600g,radeonsi: consolidate the contents of r600_resource.c
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-01-28 01:39:25 +01:00
Marek Olšák 2748b7da7e radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-01-06 18:40:41 +01:00
Andreas Hartmetz a32aa2617d radeon: Allocate htile buffer for SI in r600_texture. 2013-12-12 18:34:11 +01:00
Andreas Hartmetz ca5812b45c radeon: rearrange r600_texture and related code a bit.
This should make the differences and similarities between color and
depth buffer handling more clear.
2013-12-12 18:34:11 +01:00
Marek Olšák 0b37737cc3 winsys/radeon: set/get the scanout flag with the tiling ioctls
If we assume that all buffers allocated by the DDX are scanout, a new flag
that says "this is not scanout" has to be added to support the non-scanout
buffers and maintain backward compatibility.

This fixes bad rendering on Wayland.

The flag is defined as:
  #define RADEON_TILING_R600_NO_SCANOUT   RADEON_TILING_SWAP_16BIT

AFAIK, RADEON_TILING_SWAP_16BIT is not used on SI.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 17:26:41 +01:00
Emil Velikov 4c11099453 gallium/radeon: use PRIu64 macro for printing uint64_t
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-12-03 21:44:26 +00:00
Marek Olšák 751e8697f2 radeonsi: implement MSAA for CIK
There are also some changes to the printfs.

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23 01:54:58 +01:00
Marek Olšák 7b136de79a radeonsi: enable 2D tiling on CIK
libdrm does the DRM version check and decides if 2D tiling is used.

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23 01:54:58 +01:00
Grigori Goronzy f250fd59c4 radeon: use staging for mapping linear textures
Textures that likely reside in VRAM, are mapped for reading and
don't require direct mapping should be staged into GTT, to avoid bad
performance. This fixes readback performance of VDPAU surfaces.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-10-13 20:09:34 +02:00
Marek Olšák c7d91a6f13 r600g: fix ínitialization of non_disp_tiling flag
This fixes a regression caused by e64633e8c3
2013-10-03 18:30:49 +02:00
Marek Olšák 4e9aa6711f radeon: make texture logging more useful
This has been very useful for tracking down bugs in libdrm.

The *_PRINT_TEXDEPTH environment variables were probably never used,
so I removed them.
2013-09-29 15:18:10 +02:00
Marek Olšák e64633e8c3 r600g,radeonsi: share r600_texture.c
The function r600_choose_tiling is new and needs a review.

The only change in functionality is that it enables 2D tiling for compressed
textures on SI. It was probably accidentally turned off.

v2: don't make scanout buffers linear
2013-09-29 15:18:10 +02:00
Renamed from src/gallium/drivers/r600/r600_texture.c (Browse further)