Commit Graph

66646 Commits

Author SHA1 Message Date
Matt Turner 933c678776 i965: Initialize INTEL_DEBUG once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-01 11:32:52 -08:00
Matt Turner 82811ff176 i965: Initialize compaction tables once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-01 11:32:51 -08:00
Matt Turner 9db278d0e2 glsl: Initialize static temporaries_allocate_names once per process.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-12-01 11:32:48 -08:00
José Fonseca a5299e9e1c util/u_atomic: Fix the unlocked implementation.
It was totally broken:

- p_atomic_dec_zero() was returning the negation of the expected value

- p_atomic_inc_return()/p_atomic_dec_return() was
  post-incrementing/decrementing, hence returning the old value instead
  of the new

- p_atomic_cmpxchg() was returning the new value on success, instead of
  the old

It is clear this never used in the past. I wonder if it wouldn't be better to
yank it altogether.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-01 11:28:45 -08:00
José Fonseca ff80b92a58 util/u_atomic: Add a simple test.
It was much easier for me to verify things build and run as expected
with this simple test, than building and testing whole Mesa.

With scons the test can be build and run merely by doing:

  scons u_atomic_test

Building the test with autotools is left as a future exercise.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-01 11:28:45 -08:00
Matt Turner 6df72e970c util: Make u_atomic.h typeless.
like how C11's stdatomic.h provides generic functions. GCC's __sync_*
builtins already take a variety of types, so that's simple.

MSVC and Sun Studio don't, but we can implement it with something that
looks a little crazy but is actually quite readable.

Thanks to Jose for some MSVC fixes!

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:45 -08:00
Matt Turner 41b5858a2f util: Use stdbool.h's bool rather than "boolean".
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:45 -08:00
Matt Turner 2879a77a37 util: Remove u_atomic.h's GCC inline assembly.
GCC >= 4.1 support the __sync_* intrinsics. That seems like a
sufficiently old baseline.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:45 -08:00
Matt Turner 972f8458f1 util: Remove u_atomic.h's MSVC inline assembly.
There was already an intrinsics path that implemented all of the same
functions, plus more.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:45 -08:00
Matt Turner 504062be2a util: Remove u_atomic.h's Gallium dependence.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:45 -08:00
Matt Turner 4abd20e261 util: s/INLINE/inline/ in u_atomic.h.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:44 -08:00
Matt Turner ccad3829e3 util: Move u_atomic.h to src/util.
To be shared outside of Gallium.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-12-01 11:28:44 -08:00
Eric Anholt 3fe4d8e1e3 vc4: Introduce scheduling of QPU instructions.
This doesn't reschedule much currently, just tries to fit things into the
regfile A/B write-versus-read slots (the cause of the improvements in
shader-db), and hide texture fetch latency by scheduling setup early and
results collection late (haven't performance tested it).  This
infrastructure will be important for doing instruction pairing, though.

shader-db2 results:
total instructions in shared programs: 61874 -> 59583 (-3.70%)
instructions in affected programs:     50677 -> 48386 (-4.52%)
2014-12-01 11:00:23 -08:00
Eric Anholt 6958c404ca vc4: Drop the explicit scoreboard wait.
This is actually implicitly handled by the TLB operations.
2014-12-01 11:00:23 -08:00
Eric Anholt 334036fb64 vc4: Also deal with VPM reads at thread end.
Prevents a regression with QPU scheduling, which happens to put the no-op
reads for unused VPM contents end up at the end of the program.
2014-12-01 11:00:23 -08:00
Eric Anholt a7b1a93137 vc4: Fix assertion about SFU versus texturing.
We're supposed to be checking that nothing else writes r4, which is done
by the TMU result collection signal, not the coordinate setup.

Avoids a regression when QPU instruction scheduling is introduced.
2014-12-01 11:00:23 -08:00
Eric Anholt 2d5784c825 vc4: Add another check for invalid TLB scoreboard handling.
This was caught by an assertion in the simulator.
2014-12-01 11:00:23 -08:00
Rob Clark bb19f2c3c4 freedreno/a4xx: invalidate cache when vbo's change
Otherwise vertex shader can see stale cache data.  This in particular
happens when the same vbo is updated and reused.  Not sure yet if vbo's
at differing addresses but bound to same vertex buffer slot could have
issues, but seems safest to flush whenever new vertex buffers are bound.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-12-01 12:02:25 -05:00
Ilia Mirkin ebbd34a468 st/mesa: avoid exposing EXT_texture_integer for pre-GLSL 1.30
For drivers building up to GL(ES)3, only expose the actual extension if
the API will let it be used (e.g. via overrides/debug flags that enable
higher versions).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-11-30 13:04:29 -05:00
Ilia Mirkin 4907c31385 freedreno/a3xx: add missing integer formats and enable rendering
The mesa state tracker doesn't fall back on similar integer formats, so
they must all be provided. Remove the restriction against integer color
rendering.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:04:28 -05:00
Ilia Mirkin 82104c19f3 freedreno/a3xx: enable sampling from integer textures
We need to produce a u32 destination type on integer sampling
instructions, so keep that in a shader key set based on the
currently-bound textures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:04:28 -05:00
Ilia Mirkin 8e336ef55b freedreno: allow each generation to hook into sampler view setting
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:04:28 -05:00
Ilia Mirkin 618ff11457 freedreno/a3xx: don't use half precision shaders for int/float32
Integer outputs end up getting mangled due to cov.f32f16, and float32
loses precision. Use full precision shaders in both of those cases.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:04:28 -05:00
Ilia Mirkin f866446e8c freedreno/a3xx: disable blending for integer formats
Also add support for the BLENDABLE bind flag, similarly predicated on
non-int formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:04:28 -05:00
Ilia Mirkin 8e147e9ec8 freedreno/a3xx: remove blend clamp enables from gmem/clears
Just pass the data through unmolested. This probably has no effect since
blending isn't actually enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:00:41 -05:00
Ilia Mirkin d63afe3b58 freedreno/a3xx: add format to emit info, use to set sint/uint flags
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:00:41 -05:00
Ilia Mirkin 5d95e99622 freedreno/a3xx: add 16-bit unorm/snorm texture formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:00:41 -05:00
Ilia Mirkin 547182977f freedreno/ir3: remove unused arg parameter
Leaving it around in the struct in case we want to use it later.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-30 13:00:22 -05:00
Ilia Mirkin de83ef677f freedreno/ir3: fix UMAD
Looks like none of the mad variants do u16 * u16 + u32, so just add in
the extra value "by hand".

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
2014-11-30 13:00:22 -05:00
Rob Clark 66f694b16c freedreno/a4xx: stencil fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-30 10:44:09 -05:00
Rob Clark 5b46670487 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-30 10:44:03 -05:00
Rob Clark 3e698ebf44 freedreno/a4xx: add render target format to fd4_emit
This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-30 10:43:50 -05:00
Ilia Mirkin 4aec928ca4 freedreno/a3xx: unify vertex/texture formats into a single table
The table contains all the relevant information about each format. The
helper functions now just do lookups in the table.

Note that this adds support for a lot of formats that were previously
unsupported. Additionally it adds disabled support for integer render
buffers, which will require more work to actually enable.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-11-29 12:15:43 -05:00
Ilia Mirkin 20fbf99595 freedreno/a3xx: rename vertex/texture format enums to be more consistent
Switch both of them from independently inconsistent conventions to having
UINT/SINT/UNORM/SNORM/FLOAT/FIXED suffixes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-11-29 12:15:43 -05:00
Ilia Mirkin 3338bfcf49 freedreno/a3xx: fd3_util -> fd3_format
All the "util" helpers are actually format-related

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-11-29 12:15:43 -05:00
Ilia Mirkin 3de9fa8ff4 freedreno/a3xx: only enable blend clamp for non-float formats
This fixes arb_color_buffer_float-render GL_RGBA16F.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
2014-11-29 12:15:43 -05:00
Kenneth Graunke 67c498086d i965: Add _CACHE_ in brw_cache_id enum names.
BRW_CACHE_VS_PROG is more easily associated with program caches than
plain BRW_VS_PROG.

While we're at it, rename BRW_WM_PROG to BRW_CACHE_FS_PROG, to move away
from the outdated Windowizer/Masker name.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:47 -08:00
Kenneth Graunke e563c33d57 i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.
This flag signifies that we've emitted a new SAMPLER_STATE table.
Given that we haven't cached those in years, CACHE_NEW_SAMPLER isn't
a great name.  Putting it in the BRW_NEW_* hierarchy would make more
sense; BRW_NEW_SAMPLER_STATE_TABLE better reflects its actual purpose.

When this flag is raised, the pointer to the SAMPLER_STATE table has
changed, so we need to re-issue any packets which point to it (unit
state on Gen4-5, 3DSTATE_SAMPLER_STATE_POINTERS on Gen6, and the
per-stage variants on Gen7+).

Saves 2 * sizeof(void *) bytes per context, as we remove useless
aux_compare/aux_free function pointers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:46 -08:00
Kenneth Graunke 324368b500 i965: Move some /* CACHE_NEW_SAMPLER */ comments.
Marking brw_stage_state::sampler_count as CACHE_NEW_SAMPLER is wrong.

The number of samplers used by each program is actually computed at
draw time (brw_try_draw_prims), based purely on the currently bound
shader programs (gl_program::SamplersUsed).

CACHE_NEW_SAMPLER means that we've emitted a new SAMPLER_STATE table.
Although this could indicate that the number of samplers has changed,
it could also simply mean that the contents of the table has changed
(i.e. we've bound different textures).

The real reason these atoms depend on CACHE_NEW_SAMPLER is because they
include a pointer to the SAMPLER_STATE table.  This was not commented.

So, move the comments to the appropriate place.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:44 -08:00
Kenneth Graunke 66ebfad3cd i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.
We've been streaming these out for ages, so they basically have nothing
to do with brw_state_cache.c.

Saves 6 * sizeof(void *) bytes per context, as we won't have useless
aux_compare/aux_free functions for them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:42 -08:00
Kenneth Graunke 4d67b6ab9a i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.
These always happen together; the extra atom just means another item to
iterate through, flags to check, and a call through a function pointer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:40 -08:00
Kenneth Graunke f421db70ba i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.
On Gen4-5, unit state is specified as indirect state, rather than
commands.  If any unit state changes, we upload it via brw_state_batch
and arrange for 3DSTATE_PIPELINED_POINTERS to be re-emitted, which
updates pointers to all unit state at once.

Since there's only one command and state atom (brw_psp_urb_cs) that
needs to know about this, there's no benefit to having six separate
flags.  We can combine CACHE_NEW_*_UNIT into a single flag.

We also haven't cached these in a long time, so it doesn't make sense
to use the "CACHE_NEW_" prefix.  Instead, use the "BRW_NEW_" prefix.

This also saves 12 * sizeof(void *) bytes of memory per context, as
we remove useless aux_compare/aux_free functions for each CACHE bit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:38 -08:00
Kenneth Graunke bea9b8e306 i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order.  Some used
bonus parenthesis.  Some put multiple flags on one line, others put one
per line.  Some used tabs instead of spaces...but only on some lines.

This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.

Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-29 02:18:36 -08:00
Christoph Bumiller f3b4b263c2 nv50/ir/tgsi: handle TGSI_OPCODE_ARR
This instruction is used by st/nine.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
2014-11-28 19:17:52 -05:00
Kenneth Graunke 133280120b i965: Set prog_data->uses_kill if simulating alpha test via discards.
When using MRT on Gen4-5, we have to simulate GL's alpha test feature
by emitting discards in the fragment shader.  In this case, it makes
sense to set prog_data->uses_kill, which means the fragment shader may
kill pixels via the discard mechanism.

This saves us from having to look an extra key value in a couple of
places, including in the generator.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-27 20:25:24 -08:00
Kenneth Graunke 06372c3fa9 i965: Use brw_wm_prog_data::uses_kill, not gl_fragment_program::UsesKill
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-27 20:25:23 -08:00
Kenneth Graunke a0f8b363c0 i965/fs: Pass key->render_to_fbo via src1 of FS_OPCODE_DDY_*.
This means the generator doesn't have to look at the key, which is a
little nicer - we're pretty close to no key dependencies at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-27 20:25:19 -08:00
Kenneth Graunke cea37f0911 i965/fs: Handle derivative quality decisions in the front-end.
Kristian noted that there's very little use of brw_wm_prog_key in the
generator, and that it basically just generates what it's told, without
caring about what stage it's handling.

One exception to this is derivative handling.  When handling dFdxCoarse
and dFdxFine, we packed an enum value in a second source register,
explicitly telling the generator what to do.  For dFdx, we specified an
enum value of "please use the hint", then checked the program key in the
generator level code.

A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE}
opcodes, and have the front-end (which already decides what IR to
generate based on the program key) decide which dPdx/dPdy should
correspond to.  This consolidates the decision making in one place.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-27 20:25:14 -08:00
Kenneth Graunke 2315ae6653 i965: Create prog_data temporary variables in PS state upload code.
prog_data->foo is a bit more readable than brw->wm.prog_data->foo.
The local variable definition is also a great location to put the
obligatory /* CACHE_NEW_WM_PROG */ comment.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-11-27 20:24:24 -08:00
Kenneth Graunke 6a1c1fd503 i965: Fix missing CACHE_NEW_WM_PROG in 3DSTATE_PS_EXTRA.
brw->wm.prog_data is covered by CACHE_NEW_WM_PROG, not
BRW_NEW_FRAGMENT_PROGRAM.  So, we should listen to it.

However, I believe that BRW_NEW_FRAGMENT_PROGRAM is sufficient to cover
all the necessary cases - CACHE_NEW_WM_PROG happens in a subset of
cases.  So, the code being wrong shouldn't have triggered bugs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-11-27 20:24:15 -08:00