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freedreno/a4xx: stencil fixes 

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark 2014-11-28 11:02:20 -05:00
parent 5b46670487
commit 66f694b16c
8 changed files with 38 additions and 10 deletions
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2
src/gallium/drivers/freedreno/a4xx/fd4_draw.c
View File

@ -232,7 +232,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
} else {
OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |

3
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View File

@ -360,8 +360,9 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
OUT_RING(ring, zsa->gras_alpha_control);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, zsa->rb_stencil_control);
OUT_RING(ring, zsa->rb_stencil_control2);
OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, zsa->rb_stencilrefmask |

15
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
View File

@ -159,7 +159,7 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
@ -168,6 +168,7 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, 0xff000000 |
@ -339,7 +340,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
@ -348,6 +349,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
@ -486,12 +488,13 @@ fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
if (pfb->zsbuf) {
reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format));
}
OUT_RING(ring, reg);
if (pfb->zsbuf) {
OUT_RING(ring, A4XX_RB_DEPTH_PITCH(gmem->bin_w));
OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(gmem->bin_w));
uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
} else {
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
@ -500,7 +503,7 @@ fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
if (pfb->zsbuf) {
OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
fd_pipe2depth(pfb->zsbuf->format)));
fd4_pipe2depth(pfb->zsbuf->format)));
}
if (ctx->needs_rb_fbd) {

2
src/gallium/drivers/freedreno/a4xx/fd4_screen.c
View File

@ -73,7 +73,7 @@ fd4_screen_is_format_supported(struct pipe_screen *pscreen,
}
if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
(fd_pipe2depth(format) != ~0) &&
(fd4_pipe2depth(format) != ~0) &&
(fd4_pipe2tex(format) != ~0)) {
retval |= PIPE_BIND_DEPTH_STENCIL;
}

22
src/gallium/drivers/freedreno/a4xx/fd4_util.c
View File

@ -246,6 +246,9 @@ fd4_pipe2tex(enum pipe_format format)
case PIPE_FORMAT_I8_UNORM:
return TFMT4_NORM_UINT_8;
case PIPE_FORMAT_R8G8_UNORM:
return TFMT4_NORM_UINT_8_8;
case PIPE_FORMAT_B8G8R8A8_UNORM:
case PIPE_FORMAT_B8G8R8X8_UNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
@ -329,8 +332,9 @@ fd4_gmem_restore_format(enum pipe_format format)
switch (format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return PIPE_FORMAT_R8G8B8A8_UNORM;
case PIPE_FORMAT_Z16_UNORM:
return PIPE_FORMAT_B8G8R8A8_UNORM;
return PIPE_FORMAT_R8G8_UNORM;
default:
return format;
}
@ -368,6 +372,22 @@ fd4_pipe2swap(enum pipe_format format)
}
}
enum a4xx_depth_format
fd4_pipe2depth(enum pipe_format format)
{
switch (format) {
case PIPE_FORMAT_Z16_UNORM:
return DEPTH4_16;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
return DEPTH4_24_8;
default:
return ~0;
}
}
static inline enum a4xx_tex_swiz
tex_swiz(unsigned swiz)
{

1
src/gallium/drivers/freedreno/a4xx/fd4_util.h
View File

@ -38,6 +38,7 @@ enum a4xx_tex_fmt fd4_pipe2tex(enum pipe_format format);
enum a4xx_color_fmt fd4_pipe2color(enum pipe_format format);
enum pipe_format fd4_gmem_restore_format(enum pipe_format format);
enum a3xx_color_swap fd4_pipe2swap(enum pipe_format format);
enum a4xx_depth_format fd4_pipe2depth(enum pipe_format format);
uint32_t fd4_tex_swiz(enum pipe_format format, unsigned swizzle_r,
unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a);

2
src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
View File

@ -68,6 +68,8 @@ fd4_zsa_state_create(struct pipe_context *pctx,
A4XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
A4XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
A4XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
so->rb_stencil_control2 |=
A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER;
so->rb_stencilrefmask |=
0xff000000 | /* ??? */
A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |

1
src/gallium/drivers/freedreno/a4xx/fd4_zsa.h
View File

@ -42,6 +42,7 @@ struct fd4_zsa_stateobj {
uint32_t rb_render_control;
uint32_t rb_depth_control;
uint32_t rb_stencil_control;
uint32_t rb_stencil_control2;
uint32_t rb_stencilrefmask;
uint32_t rb_stencilrefmask_bf;
};