We used to output a VFD_FETCH entry for each VFD_DECODE, but we can
instead output just one VFD_FETCH per VBO and point multiple
VFD_DECODE entries at the same VFD_FETCH entry. There's typically
fewer VBOs than vertex elements so this is a small win in itselfs, but
more importantly, the VFD_DECODE state now only depends on program
state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
This gets us back to the behavior we used to have for freedreno: clicking
play on arm_test gets you testing of the ARM platforms that aren't under
arm-build (the LAVA runners).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Now that we have scripts in place to do baremetal testing of cheza, switch
it over. As of this writing, we have 5 chezas for baremetal and 4 for the
old docker CI setup (just 2 fewer than we originally had before this work,
since some had had filesystem failures and I switched those first), and
once we are sure of this we can backport to stable branch CI and move the
rest of them to baremetal.
I've run a lot of jobs through the baremetal scripts as I worked on
sorting out vulkan CTS stability, so I feel good about the stability of
the GLES CTS here.
The options job is now split out to separate jobs, as we don't currently
have a way to stack multiple sets deqp runs with different env vars in a
single baremetal run, and just chaining cros_servo.sh invocations runs
into a lack of cleanup of the serial-watching scripts which we rely on
container exit sorting out for us. This means a little less than 2x the
artifacts downloads we had before for a630 and a few more container
instantiations.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
This will let us:
- deploy kernels for testing code depending on new kernel featuers
- Ensure a pristine state in the HW before starting our tests
- Avoid disk rot on the chezas taking them out (we'd lost 3/9 in a few
months).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
This is a set of kernel options I've come up with mostly cribbing from
chrome os's kernel config snippet. We also build an lzma kernel, as
uncompressed kernel is big but lzma is the only compression supported by
the bootloader. With that image, we have to pack it into a FIT formatted
image+dtb blob.
CONFIG_SUNRPC_DEBUG is added so that you can set "nfsrootdebug" to figure
out what's going wrong with your nfs mount (mine were "both the tcp and
nfsvers options were required, and don't try to use 'default' as the root
path to defer to DHCP's answer because otherwise you get
/tftpboot/default, just use an empty root path which doesn't prepend
/tftpboot.")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
We won't have a user helper, so don't block for 60 seconds for it to show
up. Speeds up debug of new kernel builds.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Because some 16-bit instructions are already VOP3 on GFX10, we use
the 32-bit variants to remove the temporary VGPR and to use DDP with
the arithmetic instructions.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Some 16-bit instructions are VOP3 on GFX10 and we have to emit a
32-bit DPP mov followed by the ALU instruction.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
It is kinda surprising that
image2 = fromPlanar(image, 2, NULL)
mapImage(..., image2, ...)
does not map the third plane.
This implements that behavior in the case where the DRI frontend
lowers the multi-planar textures.
In the case it doesn't this would need driver support. AFAIU at
least etnaviv is impacted, and while it looks possible, I don't
have the etnaviv knowledge to implement it.
Instead of silently returning weird results (either always plane 0
or possibly something interleaved) this adds an error return on
mapping multi-planar textures otherwise.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5200>
Fix warning reported by Coverity.
Dereference null return value (NULL_RETURNS)
dereference: Dereferencing a pointer that might be NULL fp when calling
fwrite.
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5235>
ACO should already support Wave32 on GFX10 with all shader stages
and CTS pass. RADV currently only allows Wave32 with the compute
shader stage.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5056>
Doesn't seem to be a big win, although I could still be missing
something in my implementation. But might as well add the
documentation.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>
mesa/st is initializing pipe_shader_state for user define shaders.
This patch intialized pipe_shader_state for all passthough
and transform shaders.
This fixes crashes for several opengl apps. Issue is found in vmware
internal testing
Fixes: f01c0565bb ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5240>
Rename iris_seqno to iris_fine_fence, borrowed from si_fine_fence, to
avoid introducing any confusion with any other seqno used for tracking
pipelines.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5233>
v2: remove the option to actually request normalization and its
application in Intel < Gen6 (Jason)
v3: Also don't lower for query operations (Jason)
Fixes: 1ce8060c25
nir/lower_tex: support for lowering RECT textures
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5105>
When you're bringing up a new driver in CI with significant number of
failures (or when a CI run breaks a driver), the QPA extraction can easily
take the whole job timeout as we go about processing each QPA (100 of them
in my early VK CI fails) per unexpected result we're saving (50), which
involves reading and each line of the file in shell. By quickly filtering
out the QPA files not including our test, we can save all that shell
overhead, bringing QPA extract time down to a couple of minutes.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>
This extension only allows HLSL shader compilers to optionally embed
unambiguous type information which can be safely ignored by the driver.
This fixes a crash with the recent Vulkan backend of Path Of Exile
(it uses the extension without checking if it's supported).
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5237>
Unless we're reordering it around a barrier of the same type
No shader-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
Totals from 11 (0.01% of 127638) affected shaders:
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
Making use of the relatively recent FDO_BASE_IMAGE feature of the
templates, the x86_test-base image contents are shared as a separate
layer by the x86_test-gl/vk images (meaning the former only needs to be
downloaded once for either or both of the latter). This should be more
efficient in terms of overall network bandwidth and storage, in
particular if the base image changes less often than the -gl/vk ones.
v2:
* List x86_test-base in needs: along with x86_test-gl/vk (see parent
commit)
* Always put $STABLE/TESTING_EPHEMERAL on separate lines, will make it
easier to add any non-ephemeral packages
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>
The CS compiler now produces multiple SIMD variants, so the previous
trade-off between "always using SIMD32" and "having a smaller max
invocations" is now gone.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
This was used to decide which SIMD width to generate code for
ARB_compute_variable_group_size. Now that compiler will generate
multiple SIMD widths, this information is unused.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch. The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().
The cs_prog_data::simd_size field was removed. The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.
When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
There's an update for INTERFACE_DESCRIPTOR_DATA at dispatch, so we can
just move the KSP assignment there. This flexibility will later allow
variable group size to pick the right SIMD variant.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Kristian H. Kristensen
Eric Anholt
Samuel Pitoiset
Bas Nieuwenhuizen
Vinson Lee
Rob Clark
Neha Bhende
Chris Wilson
Gert Wollny
Rhys Perry
Michel Dänzer
Caio Marcelo de Oliveira Filho