Commit Graph

97766 Commits

Author SHA1 Message Date
Dave Airlie 06993e4ee3 r600: add support for hw atomic counters. (v3)
This adds support for the evergreen/cayman atomic counters.

These are implemented using GDS append/consume counters. The values
for each counter are loaded before drawing and saved after each draw
using special CP packets.

v2: move hw atomic assignment into driver.
v3: fix messing up caps (Gert Wollny), only store ranges in driver,
drop buffers.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
2017-11-10 08:39:36 +10:00
Dave Airlie 9e62654d4b st/mesa: add support for hw atomics to glsl->tgsi. (v5)
This adds support for creating the hw atomic tgsi from
the glsl codepaths.

v2: drop the atomic index and move to backend.
v3: drop buffer decls. (Marek)
v4: fix off by one (Gert)
v5: fix off by one the other way (Dave)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie 58d061ceef st/mesa: setup hw atomic limits. (v1.1)
HW atomics need to use caps to set some limits, and some
other limits may also need limiting.

This fixes things up to work for evergreen hw, it may need
more changes in the future if other hw wants to use this path.

v1.1: fix indent.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie 9f1db21f28 st/mesa: start adding support for hw atomics atom. (v2)
This adds a new atom that calls the new driver API to
bind buffers containing hw atomics.

v2: fixup bindings for sparse buffers. (mareko/nha)
don't bind buffer atomics when hw atomics are enabled.
use NewAtomicBuffer (mareko)

Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie e0fb6de313 mesa/program: add hw atomic counter file
This is needed for the GLSL->TGSI translation for hw atomic counters.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie cca5617348 gallium: add hw atomic buffer binding API.
This API binds atomic buffers for all bound shaders (as per the
GL semantics).

This is needed to support cross shader hw atomic counters.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie 4b0b82770a gallium/tgsi: start adding hw atomics (v3.2)
This adds support for a hw atomic counters to TGSI.

A new register file for storing atomic counters is added,
along with a new atomic counter semantic, along with docs
for both.

v2: drop semantic, move hw counter to backend,
Ilia pointed out SSO would have busted my plan, and he
was right.
v3: drop BUFFER decls. (Marek)
v3.1: minor fixups for whitespace, set ureg error
if we overflow the hw atomic limits. (nha)
v3.2: fix some docs inconsistencies (Ilia)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:35 +10:00
Dave Airlie 2a06423c00 gallium: add CAPs to support HW atomic counters. (v3)
This looks like an evergreen specific feature, but with atomic
counters AMD have hw specific counters they use instead of operating
on buffers directly. These are separate to the buffer atomics,
so require different limits and code paths.

I've left the CAP for atomic type extensible in case someone
else has a variant on this sort of thing (freedreno maybe?)
and needs to change it.

This adds all the CAPs required to add support for those atomic
counters, along with a related CAP for limiting the number of
output resources.

I'd like to land this and the st patch then I can start to
upstream the evergreen support for these and other GL4.x features.

v2: drop the ATOMIC_COUNTER_MODE cap, just use the return
from the HW counters. If 0 we use the current mode.
v3: fix some rebase errors (Gert Wollny)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:34 +10:00
Dave Airlie 24baca6e75 r600/query: drop rest of vi workaround code.
This isn't needed in r600 anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10 08:39:16 +10:00
Roland Scheidegger dd38a4ee0d docs: Fix GL_MESA_program_debug enums
13b303ff92 added the actual enums but
didn't remove the already existing XXXX ones. (And also duplicated
the "fragment" names instead of using the "vertex" names.)

Fixes: 13b303ff92 "docs: Update the list of used MESA GL enums."
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-09 23:35:12 +01:00
Brian Paul b99c6288c1 st/mesa: remove 'struct' keyword on function parameter
st_src_reg is a class, not a struct.  Simply remove 'struct' to silence
a MSVC compiler warning (class vs. struct mismatch).

Reviewed-by; Charmaine Lee <charmainel@vmware.com>
2017-11-09 14:13:59 -07:00
Brian Paul 750ee4182e threads: fix MinGW build breakage
Fixes: f1a3648784 ("threads: update for late C11 changes")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-11-09 14:13:59 -07:00
Brian Paul f8bae523d9 mesa: s/GLint/gl_buffer_index/ for _ColorDrawBufferIndexes
Also fix local variable declarations and replace -1 with BUFFER_NONE.
No Piglit changes.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-09 14:13:59 -07:00
Brian Paul 366453f4d3 mesa: s/GLint/gl_buffer_index/ for _ColorReadBufferIndex
BUFFER_NONE is -1 so no reason for GLint.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-09 14:13:59 -07:00
Brian Paul 9862a8403e mesa: minor reformatting, add const to gl_external_samplers()
This function should probably be moved elsewhere, too.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-09 14:13:59 -07:00
Brian Paul ad5f407b61 st/mesa: whitespace clean-up in st_mesa_to_tgsi.c
Remove trailing whitespace, fix indentation, wrap lines to 78 columns, etc.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-09 14:13:59 -07:00
Dylan Baker 1873327c4b meson: implement default driver arguments
This allows drivers to be set by OS/arch in a sane manner.

v2: - set _drivers to a list of drivers instead of manually assigning
      each with_*
v3: - Use "auto" instead of "default", which matches the value of other
      automatically configured options.
    - Set vulkan drivers as well
    - Add error message if no automatic drivers are known for a given
      arch/OS combo
    - use not(darwin or windows) instead of (linux or *bsd), which is
      probably more accurate (that way Solaris and other *nix systems
      aren't excluded)
    - rename softpipe to swrast, as swrast is the actual option name

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2017-11-09 13:10:59 -08:00
Kenneth Graunke 8ecdbb6136 i965: Pretend there are 4 subslices for compute shader threads on Gen9+.
Similar to what we did for pixel shader threads - see gen_device_info.c.

We don't want to bump the actual Maximum Number of Threads though, so
we adjust it here.  For pixel shaders, we don't use max_wm_threads, so
we could just bump it globally.

Supposedly fixes Piglit tests:
arb_gpu_shader_int64/execution/built-in-functions/cs-op-div-i64vec3-int64_t
arb_gpu_shader_int64/execution/built-in-functions/cs-op-div-i64vec4-int64_t
arb_gpu_shader_int64/execution/built-in-functions/cs-op-div-u64vec4-uint64_t

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-09 12:34:11 -08:00
Dylan Baker 3e9533d9b8 meson: Add script to use VERSION file for getting version
Meson has up until this point set it's version in the root meson.build
script, while the other build systems read the VERSION file. This is
just "one more thing" to duplicate between meson and every other build
system. This script is a simple "read, strip, print" sort of deal to
allow meson to read the VERSION file.

I chose to implement this in python since python is portable, and to
keep the meson.build script clean. This is also complicated by the fact
that the project() call *must* be the first non-comment,non-blank in the
toplevel meson.build script.

v2: - Move from scripts/ to bin/
    - use python explicitly to run the scripts to support windows

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-09 11:19:53 -08:00
Boris Brezillon 359a8f6ae5 broadcom/vc4: Mark BOs as purgeable when they enter the BO cache
This patch makes use of the DRM_IOCTL_VC4_GEM_MADVISE ioctl to mark all
BOs placed in the mesa BO cache as purgeable so that the system can
reclaim this memory under memory pressure.

v2:
- Removed BOs from the cache when they've been purged by the kernel
- Check whether the madvise ioctl is supported or not before using it

v3: Don't walk the whole list when we find a busy BO (by anholt, acked by
    Boris)

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-09 10:57:17 -08:00
Boris Brezillon 7d72af4f09 drm-uapi: Update vc4 header from drm-next
Taken from drm-next d65d31388a23 ("Merge tag
'drm-misc-next-fixes-2017-11-07' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")

v2: Add the NOTSUPP definition from the final drm-next version, not the
    commit (anholt).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-11-09 10:57:14 -08:00
Eric Anholt ebcb4c2156 meson: Enable VC4's NEON assembly support.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-11-09 09:40:30 -08:00
Eric Anholt 9c9fd8ff37 meson: Always link libgallium_dri.so against dep_thread.
Somehow on my cross build the -pthread is getting lost.  All the other
deps seem to work out fine.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-11-09 09:40:27 -08:00
Eric Anholt 4c94607c21 meson: Drop stale comment about making valgrind conditional.
It was fixed in 5c2ff5773a.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-11-09 09:40:25 -08:00
Eric Anholt d975e6940e meson: Leave dep_llvm empty if !with_llvm
The gallium auxiliary build would link against llvm, for the gallivm code
that it didn't build.  This broke the build on my armhf cross, where
libLLVM-3.9.so is not multiarch and thus points to x86-64 libs.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-11-09 09:40:03 -08:00
Adam Jackson 015cc6bb7c Revert "glx: Implement GLX_EXT_no_config_context (v2)"
Pushed ahead of things actually working.

This reverts commit 5293b96b16.
2017-11-09 11:41:14 -05:00
Marek Olšák 9ceb057ebf radeonsi: pack r600_surface better
160 -> 136 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
Marek Olšák 169525684f radeonsi: pack r600_texture better
1752 -> 1736 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
Marek Olšák f8a4b606a2 radeonsi: clean up r600_surface
216 -> 160 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
Marek Olšák 6916ee7e17 radeonsi: remove r600_texture::non_disp_tiling
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
Marek Olšák a06fe75eac radeonsi: remove DBG_NO_DISCARD_RANGE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
Adam Jackson 5293b96b16 glx: Implement GLX_EXT_no_config_context (v2)
This more or less ports EGL_KHR_no_config_context to GLX.

v2: Enable the extension only for those backends that support it.

Khronos: https://github.com/KhronosGroup/OpenGL-Registry/pull/102
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2017-11-09 09:35:30 -05:00
Adam Jackson 3f66d54a2a glx: Prepare the DRI backends for GLX_EXT_no_config_context
This should be safe as these backends already support the EGL version of
this extension. DRI1 is not affected because it does not support
GLX_ARB_create_context anyway. DRI-Windows is not prepared to implement
this as there's no equivalent WGL extension, and wglCreateContextAttribs
seems to really want the HDC's pixel format to be set.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-09 09:35:22 -05:00
Adam Jackson 74b701d84c glx: Relax validate_renderType_against_config for EXT_no_config_context
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2017-11-09 09:35:07 -05:00
Nicolai Hähnle ffc2060616 anv: fix build failure
Fixes: e3a8013de8 ("util/u_queue: add util_queue_fence_wait_timeout")
2017-11-09 14:49:19 +01:00
Nicolai Hähnle cc78d77043 mesa: flush and wait after creating a fallback texture
Fixes non-deterministic failures in
dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_sync.images.texture_source.teximage2d_render
and others in dEQP-EGL.functional.sharing.gles2.multithread.*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:20:58 +01:00
Nicolai Hähnle 46444613cf mesa: increase MaxServerWaitTimeout
The current value was introduced in commit a27180d0d8, which claims
that it represents ~1.11 years. However, it is interpreted in nanoseconds,
so it actually only represents ~9.8 hours. That seems a bit short.

Use the largest value consistent with both int32 and int64. It
corresponds to ~292 years in nanoseconds.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:20:58 +01:00
Nicolai Hähnle fbda7958ff st/mesa: remove redundant flushes from st_flush
st_flush should flush state tracker-internal state and the pipe, but
not mesa/main state. Of the four callers:

- glFlush/glFinish already call FLUSH_{VERTICES,STATE}.
- st_vdpau doesn't need to call them.
- st_manager will now call them explicitly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:20:58 +01:00
Nicolai Hähnle 884a0b2a9e st/dri: use stapi flush instead of pipe flush when creating fences
There may be pending operations (e.g. vertices) that need to be flushed
by the state tracker.

Found by inspection.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:20:58 +01:00
Nicolai Hähnle b921da3b74 radeonsi: use a threaded context even for debug contexts
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:04 +01:00
Nicolai Hähnle 1a6d9e087a radeonsi: record and dump time of flush
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:04 +01:00
Nicolai Hähnle b07569ad8b ddebug: optionally handle transfer commands like draws
Transfer commands can have associated GPU operations.

Enabled by passing GALLIUM_DDEBUG=transfers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle 18fd2a859d ddebug: dump context and before/after times of draws
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle ba2f2b6f2a ddebug: generalize print_named_xxx via a PRINT_NAMED macro
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle c9fefa062b ddebug: rewrite to always use a threaded approach
This patch has multiple goals:

1. Off-load the writing of records in 'always' mode to another thread
   for performance.

2. Allow using ddebug with threaded contexts. This really forces us to
   move some of the "after_draw" handling into another thread.

3. Simplify the different modes of ddebug, both in the code and in
   the user interface, i.e. GALLIUM_DDEBUG. In particular, there's
   no 'pipelined' anymore, since we're always pipelined; and 'noflush'
   is replaced by 'flush', since we no longer flush by default.

4. Fix the fences in pipelining mode. They previously relied on writes
   via pipe_context::clear_buffer. However, on radeonsi, those could
   (quite reasonably) end up in the SDMA buffer. So we use the newly
   added PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPE fences instead.

5. Improve pipelined mode overall, using the finer grained information
   provided by the new fences.

Overall, the result is that pipelined mode should be more useful, and
using ddebug in default mode is much less invasive, in the sense that
it changes the overall driver behavior less (which is kind of crucial
for a driver debugging tool).

An example of the new hang debug output:

  Gallium debugger active.
  Hang detection timeout is 1000ms.
  GPU hang detected, collecting information...

  Draw #   driver  prev BOP  TOP  BOP  dump file
  -------------------------------------------------------------
  2          YES      YES    YES  NO   /home/nha/ddebug_dumps/shader_runner_19919_00000000
  3          YES      NO     YES  NO   /home/nha/ddebug_dumps/shader_runner_19919_00000001
  4          YES      NO     YES  NO   /home/nha/ddebug_dumps/shader_runner_19919_00000002
  5          YES      NO     YES  NO   /home/nha/ddebug_dumps/shader_runner_19919_00000003

  Done.

We can see that there were almost certainly 4 draws in flight when
the hang happened: the top-of-pipe fence was signaled for all 4 draws,
the bottom-of-pipe fence for none of them. In virtually all cases,
we'd expect the first draw in the list to be at fault, but due to the
GPU parallelism, it's possible (though highly unlikely) that one of
the later draws causes a component to get stuck in a way that prevents
the earlier draws from making progress as well.

(In the above example, there were actually only 3 draws truly in flight:
the last draw is a blit that waits for the earlier draws; however, its
top-of-pipe fence is emitted before the cache flush and wait, and so
the fact that the draw hasn't truly started yet can only be seen from a
closer inspection of GPU state.)

Acked-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle e8bb8758dd ddebug: use an atomic increment when numbering files
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle d6710fe874 dd/util: extract dd_get_debug_filename_and_mkdir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:03 +01:00
Nicolai Hähnle 8491fcafab gallium/u_dump: add and use util_dump_transfer_usage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:02 +01:00
Nicolai Hähnle 9b8033a4a7 gallium/u_dump: add util_dump_ns
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:02 +01:00
Nicolai Hähnle 6f4a03b08a gallium/u_dump: export util_dump_ptr
Change format to %p while we're at it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 14:01:02 +01:00