Commit Graph

54952 Commits

Author SHA1 Message Date
Andreas Boll 6ea753b056 mesa: bump version to 9.2 (devel)
Now that branch 9.1 is created, bump the minor version in
master.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-01-31 09:01:15 +01:00
Matt Turner a527b2192e Revert "mesa: Return INVALID_OPERATION when type is known but not allowed"
This reverts commit 2906e2034c.

Fixes a regression in the glean depthStencil test.

Reverting this does not affect any tests in es3conform, so a more recent
patch must have also fixed the failure this one was intended to fix.

Reported-by: lu hua <huax.lu@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59494
2013-01-30 10:56:01 -08:00
Kenneth Graunke 7cccf46ec4 mesa: Add TexBufferRange to dispatch_sanity.
Christoph implemented this, so we should expect it to be present now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60082
2013-01-30 10:48:05 -08:00
Christoph Bumiller 4bdf5454a5 nv50,nvc0: fix/enable texture buffer objects 2013-01-30 13:10:11 +01:00
Christoph Bumiller a901d54f67 st/mesa: add support for GL_ARB_texture_buffer_range
v2: Update to handle BufferSize being -1 and return a NULL sampler
view if the specified range would cause out of bounds access.

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2013-01-30 13:10:11 +01:00
Christoph Bumiller 0fcd2c5e2f gallium: add PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-01-30 13:10:11 +01:00
Christoph Bumiller 785a8c3beb mesa: implement GL_ARB_texture_buffer_range
v2: Record texObj.BufferSize as -1 in TexBuffer(non-Range) instead
of the buffer's current size so we know we always have to use the
full size of the buffer object (i.e. even if it changes without the
user calling TexBuffer again) for the texture.

Clarify invalid offset alignment error message.

v3: Use extra GL_CORE-only section in get_hash_params.py for
TEXTURE_BUFFER_OFFSET_ALIGNMENT.

v4: Remove unnecessary check for profile in _mesa_TexBufferRange.
Add check for extension enable in get_tex_level_parameter_buffer.

v5: Fix position in gl_API.xml.
Add comment about meaning of BufferSize == -1.

v6: Add back checks for core profile and add a note about it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-30 13:10:10 +01:00
Matt Turner 02b6da1e87 build: Add missing comma in AS_IF
Reported-by: Lauri Kasanen<curaga@operamail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47248#c15
2013-01-29 13:19:18 -08:00
Brian Paul ce6bf2d4c5 mesa: remove ctx->Driver.Error() hook
Not used by any driver anymore.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-01-29 12:32:13 -07:00
Stéphane Marchesin 67e7263e45 glx: Check that swap_buffers_reply is non-NULL before using it
Check that the return value from xcb_dri2_swap_buffers_reply is
non-NULL before accessing the struct members.

Note: This is a candidate for the 9.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-01-29 11:15:22 -08:00
Brian Paul 70c5297439 mesa: fix comment typo: s/formaat/format/ 2013-01-29 11:53:24 -07:00
José Fonseca 42f762dcf6 llvmpipe: Don't advertise S8_UNORM (with feeble attempt at supporting it).
S8_UNORM was inadvertedly supported together with Z16_UNORM.

I tried to update the code to accomodate stencil-only -- it seemed a simple
thing to do -- but "fbo-stencil clear GL_STENCIL_INDEX8" still fails,
and it's not worth debugging.

Therefore although this change tries to update for S8_UNORM, it also
disables it completely.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-01-29 16:41:56 +00:00
José Fonseca 3b683700ef llvmpipe: Fix deferred depth writes for Z16_UNORM.
This special path hadn't been exercised by my earlier testing, and mask
values weren't being properly truncated to match the values.

This change fixes that.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-01-29 16:41:56 +00:00
Roland Scheidegger 0eb588a37c draw: fix draw_llvm_variant_key struct padding to avoid recompiles
The struct padding got broken by c789b981b2.
This caused serious performance regression because part of the key was
uninitialized and hence the shader always recompiled (at least on release
builds...).
While here also fix key size calculation when the number of samplers
and the number of sampler views are different.

v2: add comment

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-01-29 08:40:52 -08:00
Marek Olšák 845130951f docs/relnotes-9.1: document new features in radeon drivers 2013-01-29 17:35:17 +01:00
Brian Paul d83336ce3e docs: more VMware guest driver info, tips 2013-01-29 08:59:53 -07:00
Brian Paul c80bacba2e st/mesa: only enable GL_EXT_framebuffer_multisample if GL_MAX_SAMPLES >= 2
We never really have multisampling with one sample per pixel.
See also http://bugs.freedesktop.org/show_bug.cgi?id=59873

Note: This is a candidate for the 9.0 branch.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-01-29 08:59:53 -07:00
Brian Paul 8f3c81d018 mesa: don't enable GL_EXT_framebuffer_multisample for software drivers
Note: This is a candidate for the 9.0 branch.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-01-29 08:59:53 -07:00
Brian Paul 2180f32972 osmesa: use _mesa_generate_mipmap() for mipmap generation, not meta
See previous commit for more info.

Note: This is a candidate for the 9.0 branch.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-01-29 08:59:53 -07:00
Brian Paul 89551ae04f xlib: use _mesa_generate_mipmap() for mipmap generation, not meta
The swrast fragment program interpreter has trouble computing the
right texture LOD because it doesn't have easy access to input
derivatives.  This causes the GLSL-based meta generate mipmap code
to fetch texels from the wrong mipmap level.

One possible fix would be to set the GL_TEXTURE_MIN/MAX_LOD parameters
to limit sampling from the right level.  But let's just use the
_mesa_generate_mipmap() fallback since it's a lot faster than using
the fragment shader interpreter.

Fixes http://bugs.freedesktop.org/show_bug.cgi?id=54240

Note: This is a candidate for the 9.0 branch.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-01-29 08:59:53 -07:00
Brian Paul d60da27273 st/mesa: set ctx->Const.MaxSamples = 0, not 1
The gallium docs for pipe_screen::is_format_supported() says that
samples==0 or samples==1 both mean that multisampling is not supported.
Return GL_MAX_SAMPLES==0 instead of 1 for consistency with other drivers.

Note: This is a candidate for the 9.0 branch.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-01-29 08:59:53 -07:00
Brian Paul 4e41ae5fc1 xlib: stop use _mesa_enable_extension(), just set the boolean flags
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-01-29 08:59:53 -07:00
Brian Paul becec657d6 xlib: fix incorrect GL_ANGLE_texture_compression_dxt enable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-01-29 08:59:53 -07:00
José Fonseca 0ca384fb39 llvmpipe: Support Z16_UNORM as depth-stencil format.
Simply by adjusting the vector element width after/before
reading/writing the depth-stencil values.

Ran several GL_DEPTH_COMPONENT16 piglit tests without regressions.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-01-29 07:06:36 +00:00
Kenneth Graunke 9add4e8038 i965: Add chipset limits for Haswell GT1/GT2.
The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.

NOTE: This is a candidate for the 9.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2013-01-28 17:08:28 -08:00
Kenneth Graunke 7b07808f74 intel: Un-hardcode lengths from blitter commands.
The packet length may change at some point in the future.  Specifying it
explicitly (rather than hardcoding it in the command #define) allows us
to change it much more easily in the future.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-28 16:47:52 -08:00
Matt Turner 1b3ec16cc2 Remove APIspec.dtd
Left behind by a8ab7e33.
2013-01-28 16:48:38 -08:00
Matt Turner 6324521789 docs: List new extensions added in Mesa 9.1
I did not list the *_get_program_binary extensions since they're not
useful to anyone with their current implementation (that supports 0
binary formats).
2013-01-28 16:48:38 -08:00
Eric Anholt 99fe2b36cf intel: Use a CPU map of the batch on LLC-sharing architectures.
Before, we were keeping a CPU-only buffer to accumulate the batchbuffer in,
which was an improvement over mapping the batch through the GTT directly
(since any readback or other failure to stream through write combining
correctly would hurt).  However, on LLC-sharing architectures we can do better
by mapping the batch directly, which reduces the cache footprint of the
application since we no longer have this extra copy of a batchbuffer around.

Improves performance of GLBenchmark 2.1 offscreen on IVB by 3.5% +/- 0.4%
(n=21).  Improves Lightsmark performance by 1.1 +/- 0.1% (n=76).  Improves
cairo-gl performance by 1.9% +/- 1.4% (n=57).

No statistically significant difference in GLB2.1 on SNB (n=37).  Improves
cairo-gl performance by 2.1% +/- 0.1% (n=278).
2013-01-29 11:25:14 +11:00
Jerome Glisse e1598cb642 r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 19:09:52 -05:00
Jerome Glisse da638781f6 r600g: real fix for non 3.8 kernel
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 17:17:00 -05:00
Vinson Lee 1559994cba i965: Fix assignment instead of comparison in asserts.
Fixes side effect in assertion defects reported by Coverity.

Note: This is a candidate for the 9.1 branch.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-28 13:51:10 -08:00
Tapani Pälli 407029591c android: use gralloc_drm_get_gem_handle api
Currently a gralloc internal structure is exposed to Mesa,
Use a query function instead to maintain ABI compatibility.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-28 12:49:41 -08:00
Paul Berry 8e4bb4bc09 intel: Typo fix: "pitsh" -> "pitch"
Comment change only.
2013-01-28 12:31:25 -08:00
Jerome Glisse 72916698b0 r600g: fix segfault with old kernel
Old kernel do not have dma support, patch pushed were missing some
of the check needed to not use dma.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 14:51:40 -05:00
Zack Rusin dbb2d192de glx: only advertise GLX_INTEL_swap_event if it's supported
Only drivers supporting DRI2 version >=4 support GLX_INTEL_swap_event.
So lets mark it as such otherwise applications which use this extension
(i.e. everything based on Clutter, e.g. gnome-shell) break horribly on
drivers supporting DRI2 versions only up to 3.

Note: This is a candidate for the 9.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-01-24 19:13:05 -08:00
Vadim Girlin c9343047cf r600g: improve inputs/interpolation handling with llvm backend
Get rid of special handling for reserved regs.
Use one intrinsic for all kinds of interpolation.

v2[Vincent Lejeune]: Rebased against current master

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-01-28 18:30:38 +00:00
Tom Stellard 33dc412b89 r600g: Add ar_chan member to struct r600_bytecode
r600_bytecode::ar_chan stores the register channel for the value that
will be loaded into the AR register.

At the moment, this field is only used by the LLVM backend.  The default
backend always sets ar_chan = 0.
2013-01-28 18:30:38 +00:00
Tom Stellard 0ba0926861 r600g: More robust checks for MOVA_INT instructions 2013-01-28 18:30:37 +00:00
Vincent Lejeune a871e01174 r600g/llvm: Add dummy export for vs output
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59588

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-01-28 18:30:37 +00:00
Tom Stellard 91a160b19f r600g: Fix building with --enable-r600-llvm-compiler
https://bugs.freedesktop.org/show_bug.cgi?id=59877
2013-01-28 18:30:37 +00:00
Alex Deucher e110c98cae r600g: don't emit WAIT_UNTIL on cayman/TN (v2)
It shouldn't be needed and older kernels don't support
it.

v2: Replace with PS partial flush as before.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=59945

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-01-28 12:11:27 -05:00
Jerome Glisse 325422c494 r600g: add async for staging buffer upload v2
v2: Add virtual address to dma src/dst offset for cayman

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 11:30:35 -05:00
Jerome Glisse bff07638a8 r600g: add multi ring support with dma as first second ring v4
We keep track of ring emission order in a stack, whenever we need to
flush we empty the stack in a fifo order. There is few helpers function
for bo mapping and other ring activities that will make sure that
the ring stack is properly flush and submitted.

v2: fix st flush path, and other flush path to properly flush all
    rings if necessary
v3: - improve name of ring helpers
    - make sure that each time a cs is gona be written it endup at
      top of the stack to avoid any issue such as :
      STACK[0] = dma (withbo A,B)
      STACK[1] = gfx (withbo C,D)
      Now if code try to emit a dma command relative to bo C or D
      it will start writting cmd stream into the cs and once it
      reach the point where it adds relocation it will flush.
      At that point the cs will have cmd that don't have proper
      relocation into the relocation buffer and kernel will just
      refuse to run.
v4: - Drop the stack idea as it turn out there is no way to use it
      or benefit from it. Any time the driver start command on other
      ring, it always need to flush the previous ring. So make code
      simpler by not using a stack.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 11:30:35 -05:00
Jerome Glisse 6c064fd749 radeon/winsys: add dma ring support to winsys v3
Add ring support, you can create a cs for each ring. DMA ring is
bit special regarding relocation as you must emit as much relocation
as there is use of the buffer.

v2: - Improved comment on relocation changes
    - Use a single thread to queue cs submittion this simplify driver
      code while not impacting performances. Rational for this is that
      you have to wait for all previous submission to have completed
      so there was never a case while we could have 2 different thread
      submitting a command stream at the same time. This code just
      consolidate submission into one single thread per winsys.
v3: - Do not use semaphore for empty queue signaling, instead use
      cond var. This is because it's tricky to maintain an even number
      of call to semaphore wait and semaphore signal (the number of
      cs in the stack would for instance make that number vary).

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-01-28 11:30:35 -05:00
Roland Scheidegger cbf0f66631 gallivm,draw,llvmpipe: mass rename of unit->texture_unit/sampler_unit
Make it obvious what "unit" this is (no change in functionality).
draw still uses "unit" in places where it changes the shader by adding
texture sampling itself - it seems like this can't work with shaders
using dx10-style sample opcodes (can't mix gl-style and dx10-style
sample instructions in a shader).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-01-28 06:58:06 -08:00
Roland Scheidegger c789b981b2 gallivm: split sampler and texture state
Split the sampler interface to use separate sampler and texture (sampler_view)
state. This is needed to support dx10-style sampling instructions.
This is not quite complete since both draw/llvmpipe don't really track
textures/samplers independently yet, as well as the gallivm code not quite
using the right sampler or texture index respectively (but it should work
for the sampling codes used by opengl).
We are however losing some optimizations in the process, apply_max_lod will
no longer work, and we potentially could end up with more (unnecessary)
recompiles (if switching textures with/without mipmaps only so it shouldn't
be too bad).

v2: don't use different callback structs for sampler/sampler view functions
(which just complicates things), fix up sampling code to actually use the
right texture or sampler index, and similar for llvmpipe/draw actually
distinguish between samplers and sampler views.

v3: fix more of PIPE_MAX_SAMPLER / PIPE_MAX_SHADER_SAMPLER_VIEWS mismatches
(both in draw and llvmpipe), based on feedback from José get rid of unneeded
static sampler derived state.(which also fixes the only 2 piglit regressions
due to a forgotten assignment), fix comments based on Brian's feedback.

v4: remove some accidental unrelated whitespace changes

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-01-28 06:50:36 -08:00
Marek Olšák 87592cff57 gallium/u_upload_mgr: fix a serious memory leak
It can eat all memory and crash in a matter of minutes with r600g.
2013-01-28 02:51:52 +01:00
Christoph Bumiller e058f2ac97 nouveau: don't try to use push_data if it's not implemented 2013-01-27 13:45:06 +01:00
Matt Turner 51b64ce47b gles3: Update gl3.h
Contains a fix for Khronos bug 9557.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2013-01-26 20:42:19 -08:00