Remove the conditional break statements associated with all
terminators that are associated with a fixed iteration count,
except for the one associated with the limiting terminator.
This logic matches similiar functionality that exists in the
old GLSL IR unrolling code.
This change helps a piglit test pass on the r300 driver once
we switch off the old GLSL IR unrolling code.
Shader-db results IRIS (BDW):
total instructions in shared programs: 17538619 -> 17538595 (<.01%)
instructions in affected programs: 216 -> 192 (-11.11%)
helped: 3
HURT: 0
helped stats (abs) min: 7 max: 10 x̄: 8.00 x̃: 7
helped stats (rel) min: 10.00% max: 12.07% x̄: 11.38% x̃: 12.07%
total cycles in shared programs: 858674910 -> 858672810 (<.01%)
cycles in affected programs: 79540 -> 77440 (-2.64%)
helped: 3
HURT: 0
helped stats (abs) min: 620 max: 800 x̄: 700.00 x̃: 680
helped stats (rel) min: 2.45% max: 2.83% x̄: 2.63% x̃: 2.62%
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16399>
Previously we only cared if this was set for the limiting
terminator. However in the following patch we will make use of this
information on other terminators to decide if we can eliminate them.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16399>
Prior to scanning instrucitons, we initialize it based on variables. If
this is adding anything, we have a bug somewhere.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>
This mirrors what we do for textures. Also, the current code is busted
because it sets it based on var->data.binding which
lvp_lower_pipeline_layout will change so it can get out-of-sync.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>
Coming in from Vulkan or OpenCL, it's possible for nr_samplers to be
zero if all we ever use is texelFetch(). Annoyingly, samplers and
sampler views are handled by the same function. Fortunately, it will
work if some of the samplers or sampler views are missing so we can just
pass the maximum.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>
First, make all key_size functions take nr_samplers and nr_sampler_views
separately so we ensure both get passed in. Second, rework the offset
helpers to take MAX(nr_samplers, nr_sampler_views) so we get the image
param offset correct if nr_samplers < nr_sampler_views. While we're
here, also re-order the size calculations to be in the same order as the
things land in memory.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>
For doing performance investigation, I often find it useful to have a "are
we tripping over any of our performance TODOs?" flag, so add it and use it
in a few of the TODOs.
This also greatly cleans up the deqp-vk logs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16316>
We set the number of task shader ring entries in radv_device
based on the generous assumption that each CU can run task/mesh
shaders with maximum occupancy.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
Mostly the same as for compute shaders, but with a few extras:
task_ring_offsets:
Same as what ring_offsets is to graphics shaders.
Contains an address that points to a buffer that contains
the ring buffer descriptors.
task_ring_entry:
Index that can be used to address the draw and payload rings.
draw_id:
Same meaning as in graphics shaders.
task_ib_addr/task_ib_stride:
Indirect buffer address and stride from the draw calls.
These are used to emulate the firstTask feature of NV_mesh_shader.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
This is going to be used by both task and mesh shaders for
accessing the draw and payload ring buffers.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
Task shaders store their output payload to VRAM where mesh
shaders read from. There are two ring buffers:
1. Draw ring: this is where mesh dispatch sizes and
the ready bit are stored.
2. Payload ring: this is where the optional payload
is stored (up to 16K per task workgroup).
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
Otherwise, it would mutate `fneg(fadd(-0, 0))` into `fadd(0, -0)` which
isn't correct since -0 + (+0) = +0 + (-0) = +0.
This fixes the OpenCL contraction tests on Iris.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16041>
This may slightly increase perf somewhere because the hardware can now
pre-cache binding tables. The real feature is that INTEL_DEBUG=bat now
dumps out surface states for compute.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15759>
SM5 requires swizzles for 64 bits alu source to be either .xyzw,
.xyxy, .zwxy, or .zwzw. If the swizzles are not in the valid pattern,
move the source according to the specified swizzle to a temporary register
first.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16464>
Atomics on Valhall work basically the same as on Bifrost, however the
instruction selection is simplified as there are no clauses. Support the
simplified set of atomic instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
As opposed to LEA_ATTR_TEX. In principle we could do this for Bifrost too, but
let's keep the Midgard compatible path for now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
This should be kept to only things aco uses, and expanded when
radeonsi support is added. Things should be removed if lowered in NIR.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
Timothy Arceri
Karol Herbst
Jason Ekstrand
Emma Anholt
Timur Kristóf
Charmaine Lee
Alyssa Rosenzweig
Autumn on Tape
Corentin Noël
Dave Airlie