ac/nir: Add I/O lowering for task and mesh shaders.
Task shaders store their output payload to VRAM where mesh shaders read from. There are two ring buffers: 1. Draw ring: this is where mesh dispatch sizes and the ready bit are stored. 2. Payload ring: this is where the optional payload is stored (up to 16K per task workgroup). Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
This commit is contained in:
Timur Kristóf
Marge Bot
parent
df1876f615
commit
7de3034897
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@ -127,6 +127,19 @@ void
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ac_nir_lower_ngg_ms(nir_shader *shader,
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unsigned wave_size);
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void
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ac_nir_apply_first_task_to_task_shader(nir_shader *shader);
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void
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ac_nir_lower_task_outputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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void
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ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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nir_ssa_def *
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ac_nir_cull_triangle(nir_builder *b,
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nir_ssa_def *initially_accepted,
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@ -0,0 +1,429 @@
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/*
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* Copyright © 2022 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "ac_nir.h"
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#include "nir_builder.h"
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#include "amdgfxregs.h"
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#include "u_math.h"
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/*
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* These NIR passes are used to lower NIR cross-stage I/O intrinsics
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* between task and mesh shader stages into the memory accesses
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* that actually happen on the HW.
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*
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*/
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typedef struct {
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unsigned payload_entry_bytes;
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unsigned draw_entry_bytes;
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unsigned num_entries;
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} lower_tsms_io_state;
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typedef struct {
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nir_ssa_def *hw_workgroup_id;
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nir_ssa_def *api_workgroup_id;
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} add_first_task_to_workgroup_id_state;
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static bool filter_workgroup_id(const nir_instr *instr,
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UNUSED const void *state)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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return intrin->intrinsic == nir_intrinsic_load_workgroup_id;
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}
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static nir_ssa_def *
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replace_workgroup_id_use_first_task(nir_builder *b,
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nir_instr *instr,
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void *state)
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{
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add_first_task_to_workgroup_id_state *s = (add_first_task_to_workgroup_id_state *) state;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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assert(s->hw_workgroup_id);
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if (s->hw_workgroup_id == &intrin->dest.ssa)
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return NULL;
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return s->api_workgroup_id;
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}
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void
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ac_nir_apply_first_task_to_task_shader(nir_shader *shader)
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{
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/* The draw packets on RDNA2 GPUs don't support adding an offset to the task shader
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* workgroups, so we have to emulate the firstTask feature for NV_mesh_shader.
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*
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* 1. Pass the address of the IB (indirect buffer) from the NV_mesh_shader draw call
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* to the shader in an SGPR argument (2 SGPRs for address, 1 SGPR for stride).
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* 2. Create a descriptor for the IB in the shader.
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* 3. Load the firstTask value from the IB
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* 4. Add the firstTask value the workgroup ID and use the result instead of the
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* workgroup ID generated by the HW.
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*
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* NOTE: This pass must run _before_ lowering the task shader outputs to memory
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* accesses. The lowering uses the workgroup ID and that must be unchanged
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* because it has to be the real HW workgroup ID.
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*/
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/* If the shader doesn't use workgroup ID, nothing to do here. */
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if (!BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_WORKGROUP_ID))
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return;
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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assert(impl);
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nir_builder builder;
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nir_builder *b = &builder; /* This is to avoid the & */
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nir_builder_init(b, impl);
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b->cursor = nir_before_cf_list(&impl->body);
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/* This is the stride passed to vkCmdDrawMeshTasksIndirectNV */
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nir_ssa_def *ib_stride = nir_load_task_ib_stride(b);
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nir_ssa_def *zero = nir_imm_int(b, 0);
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nir_ssa_def *first_task = NULL;
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/* If the stride is zero, we assume that firstTask is also 0. */
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nir_if *if_stride = nir_push_if(b, nir_ine(b, ib_stride, zero));
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{
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/* Address of the IB (indirect buffer) used by the current draw call. */
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nir_ssa_def *ib_addr = nir_load_task_ib_addr(b);
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/* Compose a 64-bit address from the IB address. */
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nir_ssa_def *addr = nir_pack_64_2x32_split(b, nir_channel(b, ib_addr, 0), nir_channel(b, ib_addr, 1));
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/* The IB needs to be addressed by draw ID * stride. */
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addr = nir_iadd(b, addr, nir_u2u64(b, nir_imul(b, nir_load_draw_id(b), ib_stride)));
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/* Byte offset of the firstTask field in VkDrawMeshTasksIndirectCommandNV. */
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addr = nir_iadd_imm(b, addr, 4);
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first_task = nir_build_load_global(b, 1, 32, addr, .access = ACCESS_NON_WRITEABLE | ACCESS_COHERENT);
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}
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nir_pop_if(b, if_stride);
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first_task = nir_if_phi(b, first_task, zero);
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/* NV_mesh_shader workgroups are 1 dimensional so we only care about X here. */
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nir_ssa_def *hw_workgroup_id = nir_load_workgroup_id(b, 32);
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nir_ssa_def *api_workgroup_id_x = nir_iadd(b, nir_channel(b, hw_workgroup_id, 0), first_task);
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nir_ssa_def *api_workgroup_id = nir_vec3(b, api_workgroup_id_x, zero, zero);
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add_first_task_to_workgroup_id_state state = {
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.hw_workgroup_id = hw_workgroup_id,
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.api_workgroup_id = api_workgroup_id,
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};
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nir_shader_lower_instructions(shader,
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filter_workgroup_id,
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replace_workgroup_id_use_first_task,
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&state);
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nir_validate_shader(shader, "after including firstTask in the task shader workgroup ID");
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}
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static nir_ssa_def *
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task_workgroup_index(nir_builder *b,
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lower_tsms_io_state *s)
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{
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nir_ssa_def *id = nir_load_workgroup_id(b, 32);
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/* NV_mesh_shader: workgroups are always 1D, so index is the same as ID.x */
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return nir_channel(b, id, 0);
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}
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static nir_ssa_def *
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task_ring_entry_index(nir_builder *b,
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lower_tsms_io_state *s)
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{
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/* Task shader ring_entry shader argument:
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*
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* - It's a copy of write_ptr[31:0] from the task control buffer.
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* - The same value (which is the initial value at dispatch)
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* seems to be copied to all workgroups in the same dispatch,
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* therefore a workgroup index needs to be added.
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* - write_ptr must be initialized to num_entries so ring_entry needs
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* AND with num_entries - 1 to get the correct meaning.
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* Note that num_entries must be a power of two.
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*/
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nir_ssa_def *ring_entry = nir_load_task_ring_entry_amd(b);
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nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, task_workgroup_index(b, s));
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return nir_iand_imm(b, idx, s->num_entries - 1);
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}
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static nir_ssa_def *
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task_draw_ready_bit(nir_builder *b,
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lower_tsms_io_state *s)
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{
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/* Value of the ready bit is 1 for odd and 0 for even passes through the draw ring.
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*
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* The ring_entry is a copy of the write_ptr. We use that to determine whether
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* the current pass through the draw ring is odd or even, so we can write the
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* correct value to the draw ready bit.
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*
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* This tells the firmware that it can now start launching mesh shader workgroups.
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* The encoding of the last dword of the draw ring entry is:
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* - bit 0: Draw ready bit.
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* Its meaning flips on every pass through the entry.
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* - bit 1: Packet end bit.
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* The firmware uses this to mark the entry after the last one
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* used by the current task dispatch.
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* - bits [2:31] unused.
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*
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* Task shaders MUST write the draw ready bit to the draw ring
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* before they finish. The firmware waits for the shader to write
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* this bit before it reads the mesh dispatch size to launch the
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* mesh shader workgroups.
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*
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* If the task shader doesn't write this bit, the HW hangs.
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*/
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nir_ssa_def *ring_entry = nir_load_task_ring_entry_amd(b);
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nir_ssa_def *workgroup_index = task_workgroup_index(b, s);
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nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index);
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return nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1));
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}
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static nir_ssa_def *
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mesh_ring_entry_index(nir_builder *b,
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lower_tsms_io_state *s)
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{
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/* Mesh shader ring_entry shader argument:
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*
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* - It's a copy of the read_ptr[31:0] from the task control buffer.
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* - All workgroups in the same task->mesh dispatch get the same value,
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* which is fine because they need to read the same entry.
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* - read_ptr must be initialized to num_entries so ring_entry needs
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* AND with num_entries - 1 to get the correct meaning.
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* Note that num_entries must be a power of two.
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*/
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return nir_iand_imm(b, nir_load_task_ring_entry_amd(b), s->num_entries - 1);
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}
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static void
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task_write_draw_ring(nir_builder *b,
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nir_ssa_def *store_val,
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unsigned const_off,
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lower_tsms_io_state *s)
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{
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nir_ssa_def *ptr = task_ring_entry_index(b, s);
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nir_ssa_def *ring = nir_load_ring_task_draw_amd(b);
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nir_ssa_def *scalar_off = nir_imul_imm(b, ptr, s->draw_entry_bytes);
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nir_ssa_def *vector_off = nir_imm_int(b, 0);
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nir_store_buffer_amd(b, store_val, ring, vector_off, scalar_off,
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.base = const_off, .memory_modes = nir_var_shader_out);
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}
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static bool
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filter_task_output_or_payload(const nir_instr *instr,
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UNUSED const void *state)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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return intrin->intrinsic == nir_intrinsic_store_output ||
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intrin->intrinsic == nir_intrinsic_store_task_payload ||
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intrin->intrinsic == nir_intrinsic_load_task_payload;
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}
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static nir_ssa_def *
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lower_task_output_store(nir_builder *b,
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nir_intrinsic_instr *intrin,
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lower_tsms_io_state *s)
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{
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/* NV_mesh_shader:
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* Task shaders should only have 1 output: TASK_COUNT
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* which is the number of launched mesh shader workgroups in 1D.
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*
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* Task count is one dimensional, but the HW needs X, Y, Z.
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* Use the shader's value for X, and write Y=1, Z=1.
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*/
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nir_ssa_def *store_val = nir_vec3(b, intrin->src[0].ssa,
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nir_imm_int(b, 1),
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nir_imm_int(b, 1));
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task_write_draw_ring(b, store_val, 0, s);
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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}
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static nir_ssa_def *
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lower_task_payload_store(nir_builder *b,
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nir_intrinsic_instr *intrin,
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lower_tsms_io_state *s)
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{
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unsigned write_mask = nir_intrinsic_write_mask(intrin);
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unsigned base = nir_intrinsic_base(intrin);
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nir_ssa_def *store_val = intrin->src[0].ssa;
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nir_ssa_def *addr = intrin->src[1].ssa;
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nir_ssa_def *ring = nir_load_ring_task_payload_amd(b);
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nir_ssa_def *ptr = task_ring_entry_index(b, s);
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nir_ssa_def *ring_off = nir_imul_imm(b, ptr, s->payload_entry_bytes);
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nir_store_buffer_amd(b, store_val, ring, addr, ring_off, .base = base,
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.write_mask = write_mask,
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.memory_modes = nir_var_mem_task_payload);
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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}
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static nir_ssa_def *
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lower_taskmesh_payload_load(nir_builder *b,
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nir_intrinsic_instr *intrin,
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lower_tsms_io_state *s)
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{
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unsigned base = nir_intrinsic_base(intrin);
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unsigned num_components = intrin->dest.ssa.num_components;
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unsigned bit_size = intrin->dest.ssa.bit_size;
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nir_ssa_def *ptr =
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b->shader->info.stage == MESA_SHADER_TASK ?
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task_ring_entry_index(b, s) :
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mesh_ring_entry_index(b, s);
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nir_ssa_def *addr = intrin->src[0].ssa;
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nir_ssa_def *ring = nir_load_ring_task_payload_amd(b);
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nir_ssa_def *ring_off = nir_imul_imm(b, ptr, s->payload_entry_bytes);
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return nir_load_buffer_amd(b, num_components, bit_size, ring, addr, ring_off, .base = base,
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.memory_modes = nir_var_mem_task_payload);
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}
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static nir_ssa_def *
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lower_task_intrinsics(nir_builder *b,
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nir_instr *instr,
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void *state)
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{
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assert(instr->type == nir_instr_type_intrinsic);
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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lower_tsms_io_state *s = (lower_tsms_io_state *)state;
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if (intrin->intrinsic == nir_intrinsic_store_output)
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return lower_task_output_store(b, intrin, s);
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else if (intrin->intrinsic == nir_intrinsic_store_task_payload)
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return lower_task_payload_store(b, intrin, s);
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else if (intrin->intrinsic == nir_intrinsic_load_task_payload)
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return lower_taskmesh_payload_load(b, intrin, s);
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else
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unreachable("unsupported task shader intrinsic");
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}
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static void
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emit_task_finale(nir_builder *b, lower_tsms_io_state *s)
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{
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/* We assume there is always a single end block in the shader. */
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b->cursor = nir_after_block(nir_impl_last_block(b->impl));
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/* Wait for all task_payload, output, SSBO and global stores to finish. */
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nir_scoped_barrier(b, .execution_scope = NIR_SCOPE_WORKGROUP,
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.memory_scope = NIR_SCOPE_WORKGROUP,
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.memory_semantics = NIR_MEMORY_ACQ_REL,
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.memory_modes = nir_var_mem_task_payload | nir_var_shader_out |
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nir_var_mem_ssbo | nir_var_mem_global);
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nir_ssa_def *invocation_index = nir_load_local_invocation_index(b);
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nir_if *if_invocation_index_zero = nir_push_if(b, nir_ieq_imm(b, invocation_index, 0));
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{
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/* Write ready bit. */
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nir_ssa_def *ready_bit = task_draw_ready_bit(b, s);
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task_write_draw_ring(b, ready_bit, 12, s);
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}
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nir_pop_if(b, if_invocation_index_zero);
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}
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void
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ac_nir_lower_task_outputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries)
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{
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assert(util_is_power_of_two_nonzero(task_num_entries));
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lower_tsms_io_state state = {
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.draw_entry_bytes = 16,
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.payload_entry_bytes = task_payload_entry_bytes,
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.num_entries = task_num_entries,
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};
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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nir_builder builder;
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nir_builder *b = &builder; /* This is to avoid the & */
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nir_builder_init(b, impl);
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nir_shader_lower_instructions(shader,
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filter_task_output_or_payload,
|
||||
lower_task_intrinsics,
|
||||
&state);
|
||||
|
||||
emit_task_finale(b, &state);
|
||||
nir_metadata_preserve(impl, nir_metadata_none);
|
||||
|
||||
nir_validate_shader(shader, "after lowering task shader outputs to memory stores");
|
||||
}
|
||||
|
||||
static bool
|
||||
filter_mesh_input_load(const nir_instr *instr,
|
||||
UNUSED const void *state)
|
||||
{
|
||||
if (instr->type != nir_instr_type_intrinsic)
|
||||
return false;
|
||||
|
||||
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
||||
return intrin->intrinsic == nir_intrinsic_load_task_payload;
|
||||
}
|
||||
|
||||
static nir_ssa_def *
|
||||
lower_mesh_intrinsics(nir_builder *b,
|
||||
nir_instr *instr,
|
||||
void *state)
|
||||
{
|
||||
assert(instr->type == nir_instr_type_intrinsic);
|
||||
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
||||
lower_tsms_io_state *s = (lower_tsms_io_state *)state;
|
||||
|
||||
if (intrin->intrinsic == nir_intrinsic_load_task_payload)
|
||||
return lower_taskmesh_payload_load(b, intrin, s);
|
||||
else
|
||||
unreachable("unsupported mesh shader intrinsic");
|
||||
}
|
||||
|
||||
void
|
||||
ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
|
||||
unsigned task_payload_entry_bytes,
|
||||
unsigned task_num_entries)
|
||||
{
|
||||
assert(util_is_power_of_two_nonzero(task_num_entries));
|
||||
|
||||
lower_tsms_io_state state = {
|
||||
.draw_entry_bytes = 16,
|
||||
.payload_entry_bytes = task_payload_entry_bytes,
|
||||
.num_entries = task_num_entries,
|
||||
};
|
||||
|
||||
nir_shader_lower_instructions(shader,
|
||||
filter_mesh_input_load,
|
||||
lower_mesh_intrinsics,
|
||||
&state);
|
||||
}
|
||||
|
|
@ -96,6 +96,7 @@ amd_common_files = files(
|
|||
'ac_nir_cull.c',
|
||||
'ac_nir_lower_esgs_io_to_mem.c',
|
||||
'ac_nir_lower_global_access.c',
|
||||
'ac_nir_lower_taskmesh_io_to_mem.c',
|
||||
'ac_nir_lower_tess_io_to_mem.c',
|
||||
'ac_nir_lower_ngg.c',
|
||||
'amd_family.c',
|
||||
|
|
|
|||
|
|
@ -145,6 +145,11 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
|
|||
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
|
||||
case nir_intrinsic_load_ring_esgs_amd:
|
||||
case nir_intrinsic_load_ring_es2gs_offset_amd:
|
||||
case nir_intrinsic_load_ring_task_draw_amd:
|
||||
case nir_intrinsic_load_ring_task_payload_amd:
|
||||
case nir_intrinsic_load_task_ring_entry_amd:
|
||||
case nir_intrinsic_load_task_ib_addr:
|
||||
case nir_intrinsic_load_task_ib_stride:
|
||||
case nir_intrinsic_load_sample_positions_pan:
|
||||
case nir_intrinsic_load_workgroup_num_input_vertices_amd:
|
||||
case nir_intrinsic_load_workgroup_num_input_primitives_amd:
|
||||
|
|
|
|||
|
|
@ -1273,6 +1273,15 @@ system_value("ring_tess_factors_offset_amd", 1)
|
|||
# Descriptor where ES outputs are stored for GS to read on GFX6-8
|
||||
system_value("ring_esgs_amd", 4)
|
||||
system_value("ring_es2gs_offset_amd", 1)
|
||||
# Address of the task shader draw ring (used for VARYING_SLOT_TASK_COUNT)
|
||||
system_value("ring_task_draw_amd", 4)
|
||||
# Address of the task shader payload ring (used for all other outputs)
|
||||
system_value("ring_task_payload_amd", 4)
|
||||
# Pointer into the draw and payload rings
|
||||
system_value("task_ring_entry_amd", 1)
|
||||
# Pointer into the draw and payload rings
|
||||
system_value("task_ib_addr", 2)
|
||||
system_value("task_ib_stride", 1)
|
||||
|
||||
# Number of patches processed by each TCS workgroup
|
||||
system_value("tcs_num_patches_amd", 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue