Commit Graph

64969 Commits

Author SHA1 Message Date
Eric Anholt e2f66315cb u_vbuf: Add a few more format fallbacks.
Fixes piglit draw-vertices and gl-2.0-vertexattribpointer on vc4, where
I'm only advertising R32F to RGBA32F support so far.

Note: regresses gl-1.5-normal3b3s-invariance due to introduced flushes and
missing depth buffer load/store support in the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-24 22:13:25 -07:00
Eric Anholt bbbe3b65ad u_vbuf: Simplify the format fallback translation.
Individual caps made supporting new fallbacks more complicated than it
needed to be.  Instead, just make a table of fallbacks at context init
time.

v2: Fix inverted "do we need to install vbuf?" flagging caught by Marek.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
2014-08-24 22:13:25 -07:00
Rob Clark 306e421887 freedreno/a2xx: fix segfault
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:47 -04:00
Rob Clark bd3b096467 freedreno/a3xx: handle first/last level properly
Fixes some assumptions about first_level being zero.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:23 -04:00
Rob Clark b40a6c2b17 freedreno: implement pipe_flush_resource()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:00 -04:00
Rob Clark 478a08ebd2 freedreno: don't ignore src/dst level
Don't ignore src/dst_level in pipe_copy_region.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:08:14 -04:00
Eric Anholt 8d8a5eb792 vc4: Fix save/restore of the VS/FS in the blitter.
When I made the shader cache take the .fs member and moved the binding
point to .bind_fs, I failed to update these.  Fixes crashes in
copyteximage-related tests.
2014-08-23 16:30:42 -07:00
Eric Anholt 9542e68207 vc4: Clear padding of ioctl arguments.
Fixes valgrind complaints from valgrind being unaware of our ioctls.
2014-08-23 16:30:34 -07:00
Vinson Lee c2867f5b36 auxilary/os: Add Solaris support in os_get_total_physical_memory.
The patch fixes the build on Oracle Solaris.

  CC     os/os_misc.lo
"os/os_misc.c", line 59: #error: unexpected platform in os_sysinfo.c

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-22 18:24:34 -07:00
Alexander von Gluck IV 12a679a6f6 gallium/targets: Haiku, Fix some improper type warnings 2014-08-22 19:37:19 -04:00
Alexander von Gluck IV 31406d978d gallium/targets: Clean up Haiku softpipe renderer visual
* Drop creating gl_config first as it's only really used
  to create the state tracker visual.
2014-08-22 19:37:19 -04:00
Carl Worth 23163df24c glcpp: Don't use alternation in the lookahead for empty pragmas.
We've found that there's a buffer overrun bug in flex that's triggered by
using alternation in a lookahead pattern.

Fortunately, we don't need to match the exact {NEWLINE} expression to
detect an empty pragma. It suffices to verify that there are no non-space
characters before any newline character. So we can use a simple [\r\n] to
get the desired behavior while avoiding the flex bug.

Fixes the regression of piglit's 17000-consecutive-chars-identifier test,
(which has been crashing since commit
04e40fd337 ).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82472
Signed-off-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

CC: <mesa-stable@lists.freedesktop.org>
2014-08-22 15:14:59 -07:00
Kenneth Graunke 97d03b9366 i965: Disable try_emit_b2f_of_compare on Gen4-6.
The optimization relies on CMP setting the destination to 0, which is
equivalent to 0.0f.  However, early platforms only set the least
significant byte, leaving the other bits undefined.  So, we must disable
the optimization on those platforms.

Oddly, Sandybridge wasn't reported as broken.  The PRM states that it
only sets the LSB, but the internal documentation says that it follows
the IVB behavior.  Since it wasn't reported as broken, we believe it
really does follow the IVB behavior.

v2: Allow the optimization on Sandybridge (requested by Matt).

+32 piglits on Ironlake.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-22 11:40:32 -07:00
Matt Turner b8aa1005c8 i965/fs: Preserve CFG in predicated break pass.
Operating on this code,

B0: ...
    cmp.ne.f0(8)
    (+f0) if(8)
B1: break(8)
B2: endif(8)

We can delete B2 without attempting to merge any blocks, since the
break/continue instruction necessarily ends the previous block.

After deleting the if instruction, we attempt to merge blocks B0 and B1.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 3c4c2a6e30 i965/fs: Rename variable in predicated break pass.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 1db74a423f i965/fs: Preserve CFG in the SEL peephole.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 81755bc67b i965: Preserve CFG when deleting dead control flow.
This pass deletes an IF/ELSE/ENDIF or IF/ENDIF sequence, or the ELSE in
an ELSE/ENDIF sequence.

In the typical case (where IF and ENDIF) aren't the only instructions in
their basic blocks, we can simply remove the instructions (implicitly
deleting the block containing only the ELSE), and attempt to merge
blocks B0 and B2 together.

B0: ...
    (+f0) if(8)
B1: else(8)
B2: endif(8)
    ...

If the IF or ENDIF instructions are the only instructions in their
respective basic blocks (which are deleted by the removal of the
instructions), we'll want to instead merge the next blocks.

Both B0 and B2 are possibly removed by the removal of if & endif.
Same situation for if/endif. E.g., in the following example we'd remove
blocks B1 and B2, and then attempt to combine B0 and B3.

B0: ...
B1: (+f0) if(8)
B2: endif(8)
B3: ...

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 9cf06e27e1 i965/cfg: Add functions to combine basic blocks.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 5e6ead5e8b i965/cfg: Point to bblock_t containing associated control flow
... rather than pointing directly to the associated instruction. This
will let us set the block containing the IF statement's else-pointer to
NULL, when we delete a useless ELSE instruction, as in the case

   (+f0) if(8)
   ...
   else(8)
   endif(8)

Also, remove the pointer to the ENDIF, since it's unused, and it was
also potentially wrong, in the case of a basic block containing both an
ENDIF and an IF instruction:

   endif(8)
   cmp.ne.f0(8) ...
   (+f0) if(8)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 2a98ebd42b i965/fs: Preserve CFG in register allocation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 20a849b4aa i965: Use basic-block aware insertion/removal functions.
To avoid invalidating and recreating the control flow graph. Also stop
invalidating the CFG in places we didn't add or remove an instruction.

cfg calculations:     202951 -> 80307 (-60.43%)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner e0aa45768c i965: Add invalidate_cfg parameter to invalidate_live_intervals().
Will let us avoid invalidating the CFG if the optimization pass has
removed instructions using the new basic block methods.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner 3d6d4dc6f7 i965: Add basic-block aware backend_instruction::insert_* methods.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner dc527fbf7d i965: Add a basic-block aware backend_instruction::remove method.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Matt Turner 240adc1346 i965/cfg: Add a function to remove a block from the cfg.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Matt Turner b7d50beea4 i965/cfg: Add functions to test if a block is a successor/predecessor.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Eric Anholt e51e20c35e vc4: Add support for fragment discards.
Fixes piglit glsl-fs-discard-01 and -03, and allows a lot of mesa demos to
start running.  glsl-fs-discard-02 has a problem where the first tile is
not getting stored on the first render.
2014-08-22 10:16:58 -07:00
Eric Anholt 0f894b2795 vc4: Make some helpers for setting condition codes in instructions. 2014-08-22 10:16:58 -07:00
Eric Anholt cc68be2620 vc4: Avoid using undefined values when there's no color write.
The simulator assertion fails when you read-before-write a temporary
value, and there's no point in doing the packing if there was no color
written.
2014-08-22 10:16:58 -07:00
Eric Anholt ae83955b1d vc4: Emit the scoreboard wait just when it's needed.
This should improve performance on real hardware by allowing more shader
instances to run in parallel.  It also fixes assertion failures in tests
that don't emit a fragment color, since otherwise we didn't have enough
instructions to fit our signals in.
2014-08-22 10:16:58 -07:00
Eric Anholt c3c922289b vc4: Fix FLR for integer values less than 0.
If we didn't truncate at all, then we don't need to fix for truncation
happening in the wrong direction.

Fixes piglit builtin-functions/*-floor-*
2014-08-22 10:16:57 -07:00
Eric Anholt 2ab4e48f94 vc4: Fix totally broken assertions about inter-instruction reg conflicts.
The spec citation talked about A and B, and I proceeded to pay no
attention to whether the waddrs were for A or B.  As a result, this pair
of instructions would claim to conflict:

mov ra4, ra4 ; nop nop, r0, r0
mov.ns ra4, rb4 ; nop nop, r0, r0
2014-08-22 10:16:57 -07:00
Eric Anholt b064c9103d vc4: Add support for all the texture and FBO formats we can.
Now that tiling is in place, we can expose the other formats.  Depth is
still broken (need to make changes in the shader), but if you don't expose
it things crash all over.  SNORM is dropped, but we could re-add it later
with some shader fixes to handle converting between [0,1] and [-1,1].
2014-08-22 10:16:57 -07:00
Eric Anholt 3a1efcc7f9 vc4: Add support for texture tiling.
This still treats everything as RGBA8888 for the most part, same as
before.  This is a prerequisite for handling other texture formats, since
only RGBA8888 has a raster-layout mode.
2014-08-22 10:16:57 -07:00
Eric Anholt 1b6dcaf40c vc4: Fix a typo in the validation for miplevels.
It meant that LUMALPHA was being marked as *many* miplevels, and
unsurprisingly wouldn't validate.  On the other hand, some miplevel counts
wouldn't get the small mips validated at all.
2014-08-22 10:16:57 -07:00
Eric Anholt 74ea87cde4 vc4: Convert to using an enum for texture data types 2014-08-22 10:16:57 -07:00
Eric Anholt 1cb5cfba85 vc4: Stop complaining about unknown texture channel types.
It doesn't matter to this code -- the sampler always returns 8-bit unorm
rgba.
2014-08-22 10:16:57 -07:00
Eric Anholt b0a1e401a9 vc4: Include stdio/stdlib in headers so I don't have to include it per file.
There are a few tools I want to have always available, and fprintf() and
abort() are among them.
2014-08-22 10:16:57 -07:00
Matt Turner d77f5603a5 i965: Fix JIP/UIP calculations.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82846
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82929
2014-08-22 09:30:03 -07:00
Aaron Watry 2a553e4dc9 st/clover: Change platform name from Default to Clover
Signed-off-by: Aaron Watry <awatry at gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-08-22 10:02:31 -05:00
Emil Velikov e7f2f2dea5 dri/radeon: nuke the remaining references to sarea
Remainder of the dri1 times.

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21 21:47:44 +01:00
Emil Velikov 515ffb6c93 dri/radeon: cleanup the radeon_context vtbl
Remove the set-but-unused, and set-but-empty vtable entries.
Most likely a leftover from the dri1 days.

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21 21:47:40 +01:00
Emil Velikov dd46f0926d include: move sarea.h next to it's only user
The header is used by DRI1 drivers, which we've removed a while
back. Now only the dri1 loader in libGL is using it, so let's
move it in src/glx, and prefix it accordingly.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21 21:47:37 +01:00
Emil Velikov 7550a24fa6 dri/radeon: drop obsolete radeon_{dri,macros}.h headers
Both have been unused for at least a couple of years.
For example the last user of radeon_macros.h was removed with

commit 8c11f0a883
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Oct 14 13:27:02 2011 -0700

    radeon: Drop the legacy BO manager code.

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21 21:47:22 +01:00
Vinson Lee 1748ea8b2b SCons: Rename dri2_query_renderer.c to dri_common_query_renderer.c.
Fix SCons build error introduced with commit
3fe7daec14.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2014-08-21 12:22:18 -07:00
Connor Abbott 06ef631573 glsl/linker: pass through the is_intrinsic flag
This flag was set to true for the atomic counter intrinsics, but it
never got plumbed through the linker, so by the time it got to the
backends it would always be set to the false. The current i965 backend
code doesn't use is_intrinsic, so this should not change any existing
code, but it's useful for codepaths that want to distinguish between
intrinsics and non-intrinsics without using strcmp.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
2014-08-21 11:46:13 -07:00
Carl Worth 619505ac7c docs: Update instructions for creating a release
This captures all of the steps I have been following in making releases for
the past year or so. This way, the instructions should be sound for anyone who
would like to take over the release process going forward.
2014-08-21 10:46:02 -07:00
Roland Scheidegger eb4541ebaf llvmpipe: change LP_MAX_SHADER_INSTRUCTIONS definition
This change will double cache size for branches which have a lower
LP_MAX_SHADER_VARIANTS limit (it will not do anything on master).
The reason is that nowadays shaders tend to be quite a bit larger than they
were (they were big when llvmpipe didn't have a fs loop, got much smaller with
that loop, and since then have gradually increased quite a bit though still
smaller than without the fs loop for various reasons - among them being d3d10
compliance, usage of 8-wide vectors, non-swizzled blend code). Thus effectively
less shaders would be cached (unless they were very small and the variant limit
was hit first). Also, since we're getting rid of the IR nowadays, the cached
shaders shouldn't need all that much memory actually.
2014-08-21 19:00:29 +02:00
Carl Worth 399b4e2227 docs: Add my notes on stable-branch patch criteria
This captures the set of rules I have been using for stable-branch management,
(starting with a discussion on the mesa-dev mailing list on July 2013, and
then refined through my own experience of performing stable-branch releases
since then).
2014-08-21 09:46:57 -07:00
Carl Worth 46d03d37bf Makefile: Switch from md5sums to sha256sums
We switched to these several stable releases ago, (since the MD5 algorithm has
been broken for some time), but only now did I get around to fixing this in
the Makefile rather than just performing this step manually.

CC: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-08-21 09:05:01 -07:00