50c7aa6756
radeonsi: use si_context instead of pipe_context in parameters pt3
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
e332ba61f4
radeonsi: use si_context instead of pipe_context in parameters pt2
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
4c5efc40f4
radeonsi: update copyrights
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
e5053060eb
radeonsi: use r600_common_context less pt5
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
884fd97f6b
radeonsi: use r600_common_context less pt4
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
a8291a23c5
radeonsi: use r600_common_context less pt3
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
3069cb8b78
radeonsi: use r600_common_context less pt2
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
2b70dd8c8a
radeonsi: flatten / remove struct r600_ring
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
85e75b2da5
radeonsi: remove r600_pipe_common::blit_decompress_depth
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
e04389cc2a
radeonsi: remove r600_pipe_common::decompress_dcc
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
17e8f1608e
radeonsi: call CS flush functions directly whenever possible
...
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05 15:34:58 -04:00
eb77961292
radeonsi: add R600_DEBUG=nofmask to disable MSAA compression
...
For testing.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-02 13:55:20 -04:00
d76c204d05
util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_two_or_zero
...
The new name make the zero-input behavior more obvious. The next
patch adds a new function with different zero-input behavior.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-03-29 14:09:23 -07:00
025105453a
radeonsi: simplify DCC format categories
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-03-28 18:45:52 -04:00
769603564e
radeonsi: don't reallocate on DMABUF export if local BOs are disabled
2018-03-26 19:22:12 -04:00
f7ffa504a0
ac/surface: compute tile swizzle for GFX9
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-03-21 13:40:06 -04:00
b494ed168c
radeonsi: don't flush when si_eliminate_fast_color_clear is no-op
2018-02-21 20:03:11 +01:00
5f55f4c59f
radeonsi: make texture_discard_cmask/eliminate functions non-static
2018-02-21 20:03:11 +01:00
022c5b22fe
radeonsi: don't ignore pitch for imported textures
...
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-24 21:08:45 +01:00
986e467e4c
gallium/util: add util_num_layers helper
2017-12-25 14:23:02 +01:00
63b03dc924
gallium/util: don't pass a pipe_resource to util_resource_is_array_texture()
...
No need to pass a pipe_resource when we can just pass the target.
This makes the function potentially more usable. Rename it too.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-12 09:44:59 -07:00
010214b403
radeonsi: allow DMABUF exports for local buffers
...
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-06 15:19:02 +01:00
5e805cc74b
radeonsi: flush the context after resource_copy_region for buffer exports
...
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-12-05 13:28:00 +01:00
ed4780383c
radeonsi/gfx9: fix importing shared textures with DCC
...
VI has 11 dwords at least. GFX9 has 10 dwords.
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-30 18:46:11 +01:00
2c5f2936af
r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*
...
and handle PIPE_FLUSH_HINT_FINISH in r300.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
950221f923
radeonsi: remove r600_common_screen
...
Most files in gallium/radeon now include si_pipe.h.
chip_class and family are now here:
sscreen->info.family
sscreen->info.chip_class
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
c0d44fe0e9
radeonsi: remove query/apply_opaque_metadata callbacks
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
7aa2366b70
radeonsi: move all clear() code into si_clear.c
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
3c4d871ca2
radeonsi: enable DCC with MSAA for VI
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
373f4a48ae
radeonsi: implement fast color clear for DCC with MSAA for VI
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
e3c0a5b6e8
ac/surface: enable DCC computation for MSAA
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
6863651bbd
radeonsi: fix layered DCC fast clear
...
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
08f6b4dd7b
radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
ec15ff78c3
ac: change legacy_surf_level::slice_size to dword units
...
The next commit will reduce the size even more.
v2: typecast to uint64_t manually
v3: add more typecasts, add asserts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-27 14:44:04 +01:00
474b4a9191
ac: pack ac_surface better
...
r600_texture: 1736 -> 1488 bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-27 14:12:38 +01:00
95cd74abd4
radeonsi: remove an old hack for evergreen
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-27 14:12:38 +01:00
f8a4b606a2
radeonsi: clean up r600_surface
...
216 -> 160 bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
6916ee7e17
radeonsi: remove r600_texture::non_disp_tiling
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-09 17:32:14 +01:00
222a2fb998
util: move os_time.[ch] to src/util
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09 11:57:21 +01:00
529cdce799
radeonsi: remove 'Authors:' comments
...
It's inaccurate. Instead, see the copyright and use "git log" and
"git blame" to know the authorship.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-02 18:19:03 +01:00
07fdc0a09c
gallium: add pipe_screen::check_resource_capability
...
This is optional (and no CAP).
Implemented by radeonsi, ddebug, rbug, trace.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
76997e9133
radeonsi: shrink r600d_common.h and stop using it
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:05 +02:00
3784ce9782
radeonsi: enumerize DBG flags
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:20:16 +02:00
f1eb9a9c27
gallium/radeon: remove old r600g code checking chip_class and family
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-07 18:26:35 +02:00
4c56e07029
radeonsi: clamp depth comparison value only for fixed point formats
...
The hardware usually does this automatically. However, we upgrade
depth to Z32_FLOAT to enable TC-compatible HTILE, which means the
hardware no longer clamps the comparison value for us.
The only way to tell in the shader whether a clamp is required
seems to be to communicate an additional bit in the descriptor
table. While VI has some unused bits in the resource descriptor,
those bits have unfortunately all been used in gfx9. So we use
an unused bit in the sampler state instead.
Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f
and many other tests in dEQP-GLES3.functional.texture.shadow.*
Fixes: d4d9ec55c5
2017-09-29 11:44:50 +02:00
f70f6baaa3
gallium/radeon: consolidate PIPE_BIND_SHARED/SCANOUT handling
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-27 10:38:46 +02:00
eba2abf54b
gallium/radeon: more use of vi_dcc_formats_are_incompatible()
...
Found by inspection.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-27 09:31:24 +02:00
06bfb2d28f
r600: fork and import gallium/radeon
...
This marks the end of code sharing between r600 and radeonsi.
It's getting difficult to work on radeonsi without breaking r600.
A lot of functions had to be renamed to prevent linker conflicts.
There are also minor cleanups.
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-26 04:21:14 +02:00
a5b764cfea
radeonsi: reallocate if a non-sharable textures is being shared
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-18 17:47:49 +02:00
4bd2bdbb3c
ac/surface: add radeon_surf::has_stencil for convenience
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07 17:59:37 +02:00
Marek Olšák
Ian Romanick
Brian Paul
Nicolai Hähnle
Samuel Pitoiset